TY - GEN
T1 - A 1.5 MLIPS 40-bit AI processor
AU - Machida, Hirohisa
AU - Ando, Hideki
AU - Ikenaga, Chikako
AU - Nakashima, Hiroshi
AU - Maeda, Atsushi
AU - Nakaya, Masao
PY - 1991/12/1
Y1 - 1991/12/1
N2 - A high-performance 40-b AI (artificial intelligence) processor with a capability of 1.5 MLIPS (mega-logical-inference per second) in append has been developed. The performance of this processor is achieved by the combination of novel architectures of pipelined data typing and dereference, a 0.8-μm CMOS technology, and a clock scheme.
AB - A high-performance 40-b AI (artificial intelligence) processor with a capability of 1.5 MLIPS (mega-logical-inference per second) in append has been developed. The performance of this processor is achieved by the combination of novel architectures of pipelined data typing and dereference, a 0.8-μm CMOS technology, and a clock scheme.
UR - http://www.scopus.com/inward/record.url?scp=0026373662&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0026373662&partnerID=8YFLogxK
M3 - Conference contribution
AN - SCOPUS:0026373662
SN - 0780300157
T3 - Proceedings of the Custom Integrated Circuits Conference
BT - Proceedings of the Custom Integrated Circuits Conference
PB - Publ by IEEE
T2 - Proceedings of the IEEE 1991 Custom Integrated Circuits Conference
Y2 - 12 May 1991 through 15 May 1991
ER -