A 3.0-5.0 GHz high linearity and low power CMOS up-conversion mixer for UWB applications

S. A.Z. Murad, R. K. Pokharel, H. Kanaya, K. Yoshida

研究成果: Chapter in Book/Report/Conference proceedingConference contribution

9 被引用数 (Scopus)

抄録

This paper presents a high linearity and low power up-conversion mixer at 3.0-5.0 GHz for UWB applications in TSMC 0.18-μm CMOS technology. The design based on Gilbert-cell active double-balanced mixer using a capacitor located in parallel with the intrinsic gate-source capacitor of a transconductance stage for high linearity. The source degeneration inductors helps to improve linearity and IF input matching. The current injection is employed to increase gain and obtained low power. The up-conversion mixer converts an input of 100 MHz intermediate frequency (IF) signal to an output of 3.0-5.0 GHz radio frequency (RF) signal. The post-layout simulation results indicated that the proposed mixer achieves a higher input third order intercept point (IIP3) of 13.5-dBm, convention gain of 2.3-dB and low power of 7.1-mW at 1.2-V power supply.

本文言語英語
ホスト出版物のタイトル2010 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2010
出版社IEEE Computer Society
ISBN(印刷版)9781424499977
DOI
出版ステータス出版済み - 1 1 2010

出版物シリーズ

名前2010 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2010

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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