A 5-GHz fully integrated CMOS class-E power amplifier using self-biasing technique with cascaded class-D drivers

Yuki Yamashita, Daisuke Kanemoto, Haruichi Kanaya, Ramesh Pokharel, Keiji Yoshida

研究成果: Chapter in Book/Report/Conference proceedingConference contribution

13 被引用数 (Scopus)

抄録

This paper describes the design of 5-GHz fully integrated CMOS class-E single-ended power amplifier (PA) for wireless transmitter applications in a 0.18-μm CMOS technology. The proposed class-E PA employs the cascode topology with a self-biasing technique to reduce device stress. Three cascaded class-D driver amplifiers are used to actualize the sharp switching at the class-E power stage. All device components are integrated on chip and the chip area is 1.0×1.3 mm2. The measurement results indicate that the PA delivers 16.4 dBm output power and 35.4 % power-added efficiency with 2.3 V power supply voltage into a 50 Ω load.

本文言語英語
ホスト出版物のタイトルProceedings of the 2012 IEEE International Symposium on Radio-Frequency Integration Technology, RFIT 2012
ページ237-239
ページ数3
DOI
出版ステータス出版済み - 2012
イベント2012 IEEE International Symposium on Radio-Frequency Integration Technology, RFIT 2012 - Singapore, シンガポール
継続期間: 11 21 201211 23 2012

その他

その他2012 IEEE International Symposium on Radio-Frequency Integration Technology, RFIT 2012
Countryシンガポール
CitySingapore
Period11/21/1211/23/12

All Science Journal Classification (ASJC) codes

  • Computer Networks and Communications

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