A behavioral synthesis method with special functional units

Tsuyoshi Sadakata, Yusuke Matsunaga

研究成果: Contribution to journalArticle査読

1 被引用数 (Scopus)

抄録

This paper proposes a novel Behavioral Synthesis method that tries to reduce the number of clock cycles under clock cycle time and total functional unit area constraints using special functional units efficiently. Special functional units are designed to have shorter delay and/or smaller area than the cascaded basic functional units for specific operation patterns. For example, a Multiply-Accumulator is one of them. However, special functional units may have less flexibility for resource sharing because intermediate operation results may not be able to be obtained. Hence, almost all conventional methods can not handle special functional units efficiently for the reduction of clock cycles in practical time, especially under a tight area constraint. The proposed method makes it possible to solve module selection, scheduling, and functional unit allocation problems using special functional units in practical time with some heuristics. Experimental results show that the proposed method has achieved maximally 33% reduction of the cycles for a small application and 14% reduction for a realistic application in practical time.

本文言語英語
ページ(範囲)1084-1091
ページ数8
ジャーナルIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
E91-A
4
DOI
出版ステータス出版済み - 2008

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Computer Graphics and Computer-Aided Design
  • Applied Mathematics
  • Signal Processing

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