A bus delay reduction technique considering crosstalk

Kei Hirose, Hiroto Yasuura

研究成果: ジャーナルへの寄稿Conference article

115 引用 (Scopus)

抄録

As the CMOS technology scaled down, the horizontal coupling capacitance between adjacent wires plays a dominant part in wire load, crosstalk interference becomes a serious problem for VLSI design. We focused on the delay increase caused by crosstalk. On-chip bus delay is maximized by the crosstalk effect when adjacent wires simultaneously switch for opposite signal transition directions. This paper proposes a bus delay reduction technique by intentional skewing signal transition timing of adjacent wires. An approximated equation of bus delay shows our delay reduction technique is effective for a repeater-inserted bus. The result of SPICE simulation shows that the total bus delay reduction by from 5% to 20% can be achieved.

元の言語英語
記事番号840308
ページ(範囲)441-445
ページ数5
ジャーナルProceedings -Design, Automation and Test in Europe, DATE
DOI
出版物ステータス出版済み - 12 1 2000
イベントDesign, Automation and Test in Europe Conference and Exhibition 2000, DATE 2000 - Paris, フランス
継続期間: 3 27 20003 30 2000

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Crosstalk
Wire
Telecommunication repeaters
SPICE
Capacitance
Switches

All Science Journal Classification (ASJC) codes

  • Engineering(all)

これを引用

A bus delay reduction technique considering crosstalk. / Hirose, Kei; Yasuura, Hiroto.

:: Proceedings -Design, Automation and Test in Europe, DATE, 01.12.2000, p. 441-445.

研究成果: ジャーナルへの寄稿Conference article

@article{088547a1099d4cb8ab245602030169be,
title = "A bus delay reduction technique considering crosstalk",
abstract = "As the CMOS technology scaled down, the horizontal coupling capacitance between adjacent wires plays a dominant part in wire load, crosstalk interference becomes a serious problem for VLSI design. We focused on the delay increase caused by crosstalk. On-chip bus delay is maximized by the crosstalk effect when adjacent wires simultaneously switch for opposite signal transition directions. This paper proposes a bus delay reduction technique by intentional skewing signal transition timing of adjacent wires. An approximated equation of bus delay shows our delay reduction technique is effective for a repeater-inserted bus. The result of SPICE simulation shows that the total bus delay reduction by from 5{\%} to 20{\%} can be achieved.",
author = "Kei Hirose and Hiroto Yasuura",
year = "2000",
month = "12",
day = "1",
doi = "10.1109/DATE.2000.840308",
language = "English",
pages = "441--445",
journal = "Proceedings -Design, Automation and Test in Europe, DATE",
issn = "1530-1591",

}

TY - JOUR

T1 - A bus delay reduction technique considering crosstalk

AU - Hirose, Kei

AU - Yasuura, Hiroto

PY - 2000/12/1

Y1 - 2000/12/1

N2 - As the CMOS technology scaled down, the horizontal coupling capacitance between adjacent wires plays a dominant part in wire load, crosstalk interference becomes a serious problem for VLSI design. We focused on the delay increase caused by crosstalk. On-chip bus delay is maximized by the crosstalk effect when adjacent wires simultaneously switch for opposite signal transition directions. This paper proposes a bus delay reduction technique by intentional skewing signal transition timing of adjacent wires. An approximated equation of bus delay shows our delay reduction technique is effective for a repeater-inserted bus. The result of SPICE simulation shows that the total bus delay reduction by from 5% to 20% can be achieved.

AB - As the CMOS technology scaled down, the horizontal coupling capacitance between adjacent wires plays a dominant part in wire load, crosstalk interference becomes a serious problem for VLSI design. We focused on the delay increase caused by crosstalk. On-chip bus delay is maximized by the crosstalk effect when adjacent wires simultaneously switch for opposite signal transition directions. This paper proposes a bus delay reduction technique by intentional skewing signal transition timing of adjacent wires. An approximated equation of bus delay shows our delay reduction technique is effective for a repeater-inserted bus. The result of SPICE simulation shows that the total bus delay reduction by from 5% to 20% can be achieved.

UR - http://www.scopus.com/inward/record.url?scp=84893650459&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84893650459&partnerID=8YFLogxK

U2 - 10.1109/DATE.2000.840308

DO - 10.1109/DATE.2000.840308

M3 - Conference article

AN - SCOPUS:84893650459

SP - 441

EP - 445

JO - Proceedings -Design, Automation and Test in Europe, DATE

JF - Proceedings -Design, Automation and Test in Europe, DATE

SN - 1530-1591

M1 - 840308

ER -