TY - JOUR
T1 - A bus delay reduction technique considering crosstalk
AU - Hirose, Kei
AU - Yasuura, Hiroto
PY - 2000
Y1 - 2000
N2 - As the CMOS technology scaled down, the horizontal coupling capacitance between adjacent wires plays a dominant part in wire load, crosstalk interference becomes a serious problem for VLSI design. We focused on the delay increase caused by crosstalk. On-chip bus delay is maximized by the crosstalk effect when adjacent wires simultaneously switch for opposite signal transition directions. This paper proposes a bus delay reduction technique by intentional skewing signal transition timing of adjacent wires. An approximated equation of bus delay shows our delay reduction technique is effective for a repeater-inserted bus. The result of SPICE simulation shows that the total bus delay reduction by from 5% to 20% can be achieved.
AB - As the CMOS technology scaled down, the horizontal coupling capacitance between adjacent wires plays a dominant part in wire load, crosstalk interference becomes a serious problem for VLSI design. We focused on the delay increase caused by crosstalk. On-chip bus delay is maximized by the crosstalk effect when adjacent wires simultaneously switch for opposite signal transition directions. This paper proposes a bus delay reduction technique by intentional skewing signal transition timing of adjacent wires. An approximated equation of bus delay shows our delay reduction technique is effective for a repeater-inserted bus. The result of SPICE simulation shows that the total bus delay reduction by from 5% to 20% can be achieved.
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U2 - 10.1109/DATE.2000.840308
DO - 10.1109/DATE.2000.840308
M3 - Conference article
AN - SCOPUS:84893650459
SP - 441
EP - 445
JO - Proceedings -Design, Automation and Test in Europe, DATE
JF - Proceedings -Design, Automation and Test in Europe, DATE
SN - 1530-1591
M1 - 840308
T2 - Design, Automation and Test in Europe Conference and Exhibition 2000, DATE 2000
Y2 - 27 March 2000 through 30 March 2000
ER -