As the CMOS technology scaled down, the horizontal coupling capacitance between adjacent wires plays a dominant part in wire load, crosstalk interference becomes a serious problem for VLSI design. We focused on the delay increase caused by crosstalk. On-chip bus delay is maximized by the crosstalk effect when adjacent wires simultaneously switch for opposite signal transition directions. This paper proposes a bus delay reduction technique by intentional skewing signal transition timing of adjacent wires. An approximated equation of bus delay shows our delay reduction technique is effective for a repeater-inserted bus. The result of SPICE simulation shows that the total bus delay reduction by from 5% to 20% can be achieved.
|ジャーナル||Proceedings -Design, Automation and Test in Europe, DATE|
|出版ステータス||出版済み - 2000|
|イベント||Design, Automation and Test in Europe Conference and Exhibition 2000, DATE 2000 - Paris, フランス|
継続期間: 3月 27 2000 → 3月 30 2000
!!!All Science Journal Classification (ASJC) codes