A bus delay reduction technique considering crosstalk

Kei Hirose, Hiroto Yasuura

研究成果: Contribution to journalArticle

6 引用 (Scopus)

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Recently, progress in shrinking CMOS process technology and increasing chip size has made interconnect delay a serious problem in deep micron LSI design. The interconnect delay is maximized by the influence of crosstalk when adjacent wires simultaneously switch in opposite transient directions. This paper proposes an on-chip bus delay reduction technique based on shifting the signal transition timing of adjacent wires. From an equation for the approximate bus delay, delay reduction can be achieved by applying the proposed technique to repeater-inserted on-chip buses. The result of SPICE simulation also shows that at most a 20% reduction of the total bus delay can be achieved.

元の言語英語
ページ(範囲)24-31
ページ数8
ジャーナルElectronics and Communications in Japan, Part III: Fundamental Electronic Science (English translation of Denshi Tsushin Gakkai Ronbunshi)
85
発行部数1
DOI
出版物ステータス出版済み - 1 10 2002

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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