A CMOS attenuator with high linearity has been designed and measured in a 0.18-μm CMOS process, to be used for a variable gain amplifier of RF wireless transceiver. The design is based on four cascaded Bridge-T attenuator stages that are consecutively activated to adjust the attenuation level and improve linearity. The design operates in the frequency band of DC-2.5 GHz with 2 - 3.5 dB insertion loss and 14 dB maximum attenuation in the entire frequency range. Measured and simulated results are in good agreement over the frequency band of interest. Measured worst case S11 and S22 are -10 and -8.8 dB, respectively, across the frequency band. The measured 1-dB compression point is +22 dBm at maximum-attenuation.
|出版ステータス||出版済み - 2018|
|イベント||11th International Conference on Interdisciplinarity in Engineering, INTER-ENG 2017 - Tirgu Mures, ルーマニア|
継続期間: 10 5 2017 → 10 6 2017
All Science Journal Classification (ASJC) codes
- Industrial and Manufacturing Engineering
- Artificial Intelligence