A design for a low-power digital matched filter applicable to W-CDMA

S. Goto, T. Yamada, N. Takayama, Hiroto Yasuura, Yoshifurni Matsushita, Yasoo Harada

研究成果: 著書/レポートタイプへの貢献会議での発言

8 引用 (Scopus)

抄録

This paper presents a design for a low-power digital matched filter (DMF) applicable to Wideband-Code Division Multiple Access (W-CDMA), which is a Direct-Sequence Spread-Spectrum (DS-SS) communication system. The proposed architectural approach to reducing the power consumption focuses on the reception registers and the correlation-calculating unit (CCU), which dissipate the majority of the power in a DMF The main features are asynchronous latch clock generation for the reception registers, parallelism of the correlation calculation operations and bit manipulation for chip-correlation operations. A DMF is designed in compliance with the W-CDMA specifications incorporating the proposed techniques, and its properties are evaluated by computer simulations at the gate level using 0.18-μm CMOS standard cell array technology. The results of the simulations show a power consumption of 9.3 mW (@15.6MHz, 1.6V), which is only about 30% of the power consumption of conventional DMFs.

元の言語英語
ホスト出版物のタイトルProceedings - Euromicro Symposium on Digital System Design
ホスト出版物のサブタイトルArchitectures, Methods and Tools, DSD 2002
編集者Martyn Edwards
出版者Institute of Electrical and Electronics Engineers Inc.
ページ210-217
ページ数8
ISBN(電子版)0769517900, 9780769517902
DOI
出版物ステータス出版済み - 1 1 2002
イベントEuromicro Symposium on Digital System Design, DSD 2002 - Dortmund, ドイツ
継続期間: 9 4 20029 6 2002

出版物シリーズ

名前Proceedings - Euromicro Symposium on Digital System Design: Architectures, Methods and Tools, DSD 2002

その他

その他Euromicro Symposium on Digital System Design, DSD 2002
ドイツ
Dortmund
期間9/4/029/6/02

Fingerprint

Matched filters
Digital filters
Code division multiple access
Electric power utilization
Flip flop circuits
Clocks
Communication systems
Specifications
Computer simulation

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Hardware and Architecture

これを引用

Goto, S., Yamada, T., Takayama, N., Yasuura, H., Matsushita, Y., & Harada, Y. (2002). A design for a low-power digital matched filter applicable to W-CDMA. : M. Edwards (版), Proceedings - Euromicro Symposium on Digital System Design: Architectures, Methods and Tools, DSD 2002 (pp. 210-217). [1115371] (Proceedings - Euromicro Symposium on Digital System Design: Architectures, Methods and Tools, DSD 2002). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/DSD.2002.1115371

A design for a low-power digital matched filter applicable to W-CDMA. / Goto, S.; Yamada, T.; Takayama, N.; Yasuura, Hiroto; Matsushita, Yoshifurni; Harada, Yasoo.

Proceedings - Euromicro Symposium on Digital System Design: Architectures, Methods and Tools, DSD 2002. 版 / Martyn Edwards. Institute of Electrical and Electronics Engineers Inc., 2002. p. 210-217 1115371 (Proceedings - Euromicro Symposium on Digital System Design: Architectures, Methods and Tools, DSD 2002).

研究成果: 著書/レポートタイプへの貢献会議での発言

Goto, S, Yamada, T, Takayama, N, Yasuura, H, Matsushita, Y & Harada, Y 2002, A design for a low-power digital matched filter applicable to W-CDMA. : M Edwards (版), Proceedings - Euromicro Symposium on Digital System Design: Architectures, Methods and Tools, DSD 2002., 1115371, Proceedings - Euromicro Symposium on Digital System Design: Architectures, Methods and Tools, DSD 2002, Institute of Electrical and Electronics Engineers Inc., pp. 210-217, Euromicro Symposium on Digital System Design, DSD 2002, Dortmund, ドイツ, 9/4/02. https://doi.org/10.1109/DSD.2002.1115371
Goto S, Yamada T, Takayama N, Yasuura H, Matsushita Y, Harada Y. A design for a low-power digital matched filter applicable to W-CDMA. : Edwards M, 編集者, Proceedings - Euromicro Symposium on Digital System Design: Architectures, Methods and Tools, DSD 2002. Institute of Electrical and Electronics Engineers Inc. 2002. p. 210-217. 1115371. (Proceedings - Euromicro Symposium on Digital System Design: Architectures, Methods and Tools, DSD 2002). https://doi.org/10.1109/DSD.2002.1115371
Goto, S. ; Yamada, T. ; Takayama, N. ; Yasuura, Hiroto ; Matsushita, Yoshifurni ; Harada, Yasoo. / A design for a low-power digital matched filter applicable to W-CDMA. Proceedings - Euromicro Symposium on Digital System Design: Architectures, Methods and Tools, DSD 2002. 編集者 / Martyn Edwards. Institute of Electrical and Electronics Engineers Inc., 2002. pp. 210-217 (Proceedings - Euromicro Symposium on Digital System Design: Architectures, Methods and Tools, DSD 2002).
@inproceedings{6dfb625b6a4e423180ef700527e3faa4,
title = "A design for a low-power digital matched filter applicable to W-CDMA",
abstract = "This paper presents a design for a low-power digital matched filter (DMF) applicable to Wideband-Code Division Multiple Access (W-CDMA), which is a Direct-Sequence Spread-Spectrum (DS-SS) communication system. The proposed architectural approach to reducing the power consumption focuses on the reception registers and the correlation-calculating unit (CCU), which dissipate the majority of the power in a DMF The main features are asynchronous latch clock generation for the reception registers, parallelism of the correlation calculation operations and bit manipulation for chip-correlation operations. A DMF is designed in compliance with the W-CDMA specifications incorporating the proposed techniques, and its properties are evaluated by computer simulations at the gate level using 0.18-μm CMOS standard cell array technology. The results of the simulations show a power consumption of 9.3 mW (@15.6MHz, 1.6V), which is only about 30{\%} of the power consumption of conventional DMFs.",
author = "S. Goto and T. Yamada and N. Takayama and Hiroto Yasuura and Yoshifurni Matsushita and Yasoo Harada",
year = "2002",
month = "1",
day = "1",
doi = "10.1109/DSD.2002.1115371",
language = "English",
series = "Proceedings - Euromicro Symposium on Digital System Design: Architectures, Methods and Tools, DSD 2002",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "210--217",
editor = "Martyn Edwards",
booktitle = "Proceedings - Euromicro Symposium on Digital System Design",
address = "United States",

}

TY - GEN

T1 - A design for a low-power digital matched filter applicable to W-CDMA

AU - Goto, S.

AU - Yamada, T.

AU - Takayama, N.

AU - Yasuura, Hiroto

AU - Matsushita, Yoshifurni

AU - Harada, Yasoo

PY - 2002/1/1

Y1 - 2002/1/1

N2 - This paper presents a design for a low-power digital matched filter (DMF) applicable to Wideband-Code Division Multiple Access (W-CDMA), which is a Direct-Sequence Spread-Spectrum (DS-SS) communication system. The proposed architectural approach to reducing the power consumption focuses on the reception registers and the correlation-calculating unit (CCU), which dissipate the majority of the power in a DMF The main features are asynchronous latch clock generation for the reception registers, parallelism of the correlation calculation operations and bit manipulation for chip-correlation operations. A DMF is designed in compliance with the W-CDMA specifications incorporating the proposed techniques, and its properties are evaluated by computer simulations at the gate level using 0.18-μm CMOS standard cell array technology. The results of the simulations show a power consumption of 9.3 mW (@15.6MHz, 1.6V), which is only about 30% of the power consumption of conventional DMFs.

AB - This paper presents a design for a low-power digital matched filter (DMF) applicable to Wideband-Code Division Multiple Access (W-CDMA), which is a Direct-Sequence Spread-Spectrum (DS-SS) communication system. The proposed architectural approach to reducing the power consumption focuses on the reception registers and the correlation-calculating unit (CCU), which dissipate the majority of the power in a DMF The main features are asynchronous latch clock generation for the reception registers, parallelism of the correlation calculation operations and bit manipulation for chip-correlation operations. A DMF is designed in compliance with the W-CDMA specifications incorporating the proposed techniques, and its properties are evaluated by computer simulations at the gate level using 0.18-μm CMOS standard cell array technology. The results of the simulations show a power consumption of 9.3 mW (@15.6MHz, 1.6V), which is only about 30% of the power consumption of conventional DMFs.

UR - http://www.scopus.com/inward/record.url?scp=84949675942&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84949675942&partnerID=8YFLogxK

U2 - 10.1109/DSD.2002.1115371

DO - 10.1109/DSD.2002.1115371

M3 - Conference contribution

T3 - Proceedings - Euromicro Symposium on Digital System Design: Architectures, Methods and Tools, DSD 2002

SP - 210

EP - 217

BT - Proceedings - Euromicro Symposium on Digital System Design

A2 - Edwards, Martyn

PB - Institute of Electrical and Electronics Engineers Inc.

ER -