TY - GEN
T1 - A design for a low-power digital matched filter applicable to W-CDMA
AU - Goto, S.
AU - Yamada, T.
AU - Takayama, N.
AU - Yasuura, H.
AU - Matsushita, Yoshifurni
AU - Harada, Yasoo
N1 - Publisher Copyright:
© 2002 IEEE.
Copyright:
Copyright 2015 Elsevier B.V., All rights reserved.
PY - 2002
Y1 - 2002
N2 - This paper presents a design for a low-power digital matched filter (DMF) applicable to Wideband-Code Division Multiple Access (W-CDMA), which is a Direct-Sequence Spread-Spectrum (DS-SS) communication system. The proposed architectural approach to reducing the power consumption focuses on the reception registers and the correlation-calculating unit (CCU), which dissipate the majority of the power in a DMF The main features are asynchronous latch clock generation for the reception registers, parallelism of the correlation calculation operations and bit manipulation for chip-correlation operations. A DMF is designed in compliance with the W-CDMA specifications incorporating the proposed techniques, and its properties are evaluated by computer simulations at the gate level using 0.18-μm CMOS standard cell array technology. The results of the simulations show a power consumption of 9.3 mW (@15.6MHz, 1.6V), which is only about 30% of the power consumption of conventional DMFs.
AB - This paper presents a design for a low-power digital matched filter (DMF) applicable to Wideband-Code Division Multiple Access (W-CDMA), which is a Direct-Sequence Spread-Spectrum (DS-SS) communication system. The proposed architectural approach to reducing the power consumption focuses on the reception registers and the correlation-calculating unit (CCU), which dissipate the majority of the power in a DMF The main features are asynchronous latch clock generation for the reception registers, parallelism of the correlation calculation operations and bit manipulation for chip-correlation operations. A DMF is designed in compliance with the W-CDMA specifications incorporating the proposed techniques, and its properties are evaluated by computer simulations at the gate level using 0.18-μm CMOS standard cell array technology. The results of the simulations show a power consumption of 9.3 mW (@15.6MHz, 1.6V), which is only about 30% of the power consumption of conventional DMFs.
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U2 - 10.1109/DSD.2002.1115371
DO - 10.1109/DSD.2002.1115371
M3 - Conference contribution
AN - SCOPUS:84949675942
T3 - Proceedings - Euromicro Symposium on Digital System Design: Architectures, Methods and Tools, DSD 2002
SP - 210
EP - 217
BT - Proceedings - Euromicro Symposium on Digital System Design
A2 - Edwards, Martyn
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - Euromicro Symposium on Digital System Design, DSD 2002
Y2 - 4 September 2002 through 6 September 2002
ER -