A design methodology for SAR ADC optimal redundancy bit

Toru Okazaki, Daisuke Kanemoto, Ramesh Pokharel, Keiji Yoshida, Haruichi Kanaya

研究成果: ジャーナルへの寄稿レター

1 引用 (Scopus)

抄録

This paper presents a design method of SAR ADC (Successive Approximation Register Analog-to-Digital Converter ADC) utilizing redundancy bits. In general, binary search algorithm is used as a conventional SAR ADC operation algorithm. It's possible to realize a high-speed SAR ADC by using non-binary search algorithm which is realized by adding redundancy bits. However, the A/D conversion time varies depending on the number of redundancy bits. Therefore, in order that the conversion time is the shortest, it's necessary that an appropriate amount of redundancy be added. We show a methodology of finding the appropriate number of redundancy bits.

元の言語英語
ジャーナルIEICE Electronics Express
11
発行部数10
DOI
出版物ステータス出版済み - 2014

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redundancy
Redundancy
methodology
registers
analog to digital converters
Digital to analog conversion
high speed
approximation

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering

これを引用

A design methodology for SAR ADC optimal redundancy bit. / Okazaki, Toru; Kanemoto, Daisuke; Pokharel, Ramesh; Yoshida, Keiji; Kanaya, Haruichi.

:: IEICE Electronics Express, 巻 11, 番号 10, 2014.

研究成果: ジャーナルへの寄稿レター

Okazaki, Toru ; Kanemoto, Daisuke ; Pokharel, Ramesh ; Yoshida, Keiji ; Kanaya, Haruichi. / A design methodology for SAR ADC optimal redundancy bit. :: IEICE Electronics Express. 2014 ; 巻 11, 番号 10.
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