A flexible hardware barrier mechanism for many-core processors

Takeshi Soga, Hiroshi Sasaki, Tomoya Hirao, Masaaki Kondo, Koji Inoue

研究成果: Chapter in Book/Report/Conference proceedingConference contribution

3 被引用数 (Scopus)

抄録

This paper proposes a new hardware barrier mechanism which offers the flexibility to select which cores should join the synchronization, allowing for executing multiple multi-threaded applications by dividing a many-core processor into several groups. Experimental results based on an RTL simulation show that our hardware barrier achieves a 66-fold reduction in latency over typical software based implementations, with a hardware overhead of the processor of only 1.8%. Additionally, we demonstrate that the proposed mechanism is sufficiently flexible to cover a variety of core groups with minimal hardware overhead.

本文言語英語
ホスト出版物のタイトル20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015
出版社Institute of Electrical and Electronics Engineers Inc.
ページ61-68
ページ数8
ISBN(電子版)9781479977925
DOI
出版ステータス出版済み - 3 11 2015
イベント2015 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015 - Chiba, 日本
継続期間: 1 19 20151 22 2015

出版物シリーズ

名前20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015

その他

その他2015 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015
国/地域日本
CityChiba
Period1/19/151/22/15

All Science Journal Classification (ASJC) codes

  • コンピュータ サイエンスの応用
  • 電子工学および電気工学
  • 制御およびシステム工学
  • モデリングとシミュレーション

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