A Hardware Maze Router with Application to Interactive Rip-Up and Reroute

Kei Suzuki, Yusuke Matsunaga, Masayoshi Tachibana, Tatsuo Ohtsuki

研究成果: ジャーナルへの寄稿記事

13 引用 (Scopus)

抄録

This paper presents a new parallel-processing architecture for hardware routers based on the Lee algorithm. Unlike the existing machines, which require N2 processors to implement the Lee algorithm on an N x N grid plane, the proposed architecture requires only O(N) processors to find a path in O(N) time. A prototype machine with 64 processors has been developed to deal with a 128 × 128 grid plane. The architecture of the machine is discussed, together with its experimental performance data. Further, it is reported that the parallel-processed Lee algorithm is most useful and powerful when applied to interactive rip-up and reroute.

元の言語英語
ページ(範囲)466-476
ページ数11
ジャーナルIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
5
発行部数4
DOI
出版物ステータス出版済み - 1 1 1986
外部発表Yes

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Routers
Hardware
Processing

All Science Journal Classification (ASJC) codes

  • Software
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

これを引用

A Hardware Maze Router with Application to Interactive Rip-Up and Reroute. / Suzuki, Kei; Matsunaga, Yusuke; Tachibana, Masayoshi; Ohtsuki, Tatsuo.

:: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 巻 5, 番号 4, 01.01.1986, p. 466-476.

研究成果: ジャーナルへの寄稿記事

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