A Hardware Maze Router with Application to Interactive Rip-Up and Reroute

Kei Suzuki, Yusuke Matsunaga, Masayoshi Tachibana, Tatsuo Ohtsuki

研究成果: Contribution to journalArticle査読

13 被引用数 (Scopus)

抄録

This paper presents a new parallel-processing architecture for hardware routers based on the Lee algorithm. Unlike the existing machines, which require N2 processors to implement the Lee algorithm on an N x N grid plane, the proposed architecture requires only O(N) processors to find a path in O(N) time. A prototype machine with 64 processors has been developed to deal with a 128 × 128 grid plane. The architecture of the machine is discussed, together with its experimental performance data. Further, it is reported that the parallel-processed Lee algorithm is most useful and powerful when applied to interactive rip-up and reroute.

本文言語英語
ページ(範囲)466-476
ページ数11
ジャーナルIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
5
4
DOI
出版ステータス出版済み - 10 1986
外部発表はい

All Science Journal Classification (ASJC) codes

  • Software
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

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