A high-performance/low-power on-chip memory-path architecture with variable cache-line size

Inoue Koji, Koji Kai, Kazuaki Murakami

研究成果: Contribution to journalArticle査読

5 被引用数 (Scopus)

抄録

This paper proposes an on-chip memory-path architecture employing the dynamically variable line-size (D-VLS) cache for high performance and low energy consumption. The D-VLS cache exploits the high on-chip memory bandwidth attainable on merged DRAM/logic LSIs by replacing a whole large cache line in one cycle. At the same time, it attempts to avoid frequent evictions by decreasing the cache-line size when programs have poor spatial locality. Activating only on-chip DRAM subarrays corresponding to a replaced cache-line size produces a significant energy reduction. In our simulation, it is observed that our proposed on-chip memory-path architecture, which employs a direct-mapped D-VLS cache, improves the ED (Energy Delay) product by more than 75% over a conventional memory-path model.

本文言語英語
ページ(範囲)1716-1722
ページ数7
ジャーナルIEICE Transactions on Electronics
E83-C
11
出版ステータス出版済み - 2000

All Science Journal Classification (ASJC) codes

  • 電子工学および電気工学

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