A low energy set-associative I-cache with extended BTB

Koji Inoue, Vasily G. Moshnyaga, Kazuaki Murakami

研究成果: Contribution to journalArticle査読

7 被引用数 (Scopus)

抄録

This paper proposes a low-energy instruction-cache architecture, called history-based tag-comparison (HBTC) cache. The HBTC cache attempts to re-use tag-comparison results for avoiding unnecessary way activation in set-associative caches. The cache records tag-comparison results in an extended BTB, and re-uses them for directly selecting only the hit-way which includes the target instruction. In our simulation, it is observed that the HBTC cache can achieve 62% of energy reduction, with less than 1% performance degradation, compared with a conventional cache.

本文言語英語
論文番号32
ページ(範囲)187-192
ページ数6
ジャーナルProceedings-IEEE International Conference on Computer Design: VLSI in Computers and Processors
DOI
出版ステータス出版済み - 1 1 2002
外部発表はい

All Science Journal Classification (ASJC) codes

  • ハードウェアとアーキテクチャ
  • 電子工学および電気工学

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