A low-glitch and small-logic-area Fibonacci Series DAC

Kazuya Hokazono, Daisuke Kanemoto, Ramesh Pokharel, Abhishek Tomar, Haruichi Kanaya, Keiji Yoshida

研究成果: Chapter in Book/Report/Conference proceedingConference contribution

5 被引用数 (Scopus)

抄録

A novel Digital-to-Analog Converter (DAC) utilizing Fibonacci Series is presented in this paper. The ratios of successive weights are smaller than those of binary DAC and larger than those of unary DAC. The features of the proposed DAC are lower glitch-energy than a binary DAC and the number of logic gates is less than a unary DAC. In the proposed DAC in 0.18μm CMOS process, the glitch-energy of the proposed DAC can be reduced by 75% compared to that of binary DAC, and the number of logic gates can be achieved an around 42% reduction compared to that of the unary DAC. We fabricated a prototype 6-bit Fibonacci Series DAC in order to confirm the operation.

本文言語英語
ホスト出版物のタイトル54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011
DOI
出版ステータス出版済み - 10 13 2011
イベント54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011 - Seoul, 大韓民国
継続期間: 8 7 20118 10 2011

出版物シリーズ

名前Midwest Symposium on Circuits and Systems
ISSN(印刷版)1548-3746

その他

その他54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011
Country大韓民国
CitySeoul
Period8/7/118/10/11

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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