A low-power and GHz-Band LC-DCO directly drives 10mm on-chip clock distribution line in 0.18 μm CMOS

Masahiro Ichihashi, Haruichi Kanaya

研究成果: ジャーナルへの寄稿記事

抄録

High-speed clock distribution design is becoming increasingly difficult and challenging task due to the huge power consumption and jitter caused by large capacitive loading and multiple repeater stages. This paper proposes a novel low-power, GHz-band bufferless LC-DCO which directly drives 10 mm on-chip clock distribution line for high-speed serial links. The shared LC-tank structure between DCO frequency tuning capacitor and clock distribution line mitigate the frequency sensitivity and makes an energy-efficient, area-saving, high-speed operation possible. The test-chip is implemented under TSMC 0.18 μm, 1-poly, 6-metal CMOS technology and the core area of proposed LC-DCO is only 270 × 280 μm2. The full-chip post layout simulation results show 2.54 GHz oscillation frequency, 2.2mA current consumption and phase noise of -123 dBc/Hz at 1MHz offset.

元の言語英語
ページ(範囲)1907-1914
ページ数8
ジャーナルIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
E101A
発行部数11
DOI
出版物ステータス出版済み - 11 1 2018

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Clocks
High Speed
Chip
Line
Phase Noise
Telecommunication repeaters
Jitter
Phase noise
Capacitor
Energy Efficient
Power Consumption
Layout
Tuning
Electric power utilization
Capacitors
Metals
Oscillation
Simulation
Design
Mm

All Science Journal Classification (ASJC) codes

  • Signal Processing
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering
  • Applied Mathematics

これを引用

@article{a00cd0b471464a38b9f55e267f99a886,
title = "A low-power and GHz-Band LC-DCO directly drives 10mm on-chip clock distribution line in 0.18 μm CMOS",
abstract = "High-speed clock distribution design is becoming increasingly difficult and challenging task due to the huge power consumption and jitter caused by large capacitive loading and multiple repeater stages. This paper proposes a novel low-power, GHz-band bufferless LC-DCO which directly drives 10 mm on-chip clock distribution line for high-speed serial links. The shared LC-tank structure between DCO frequency tuning capacitor and clock distribution line mitigate the frequency sensitivity and makes an energy-efficient, area-saving, high-speed operation possible. The test-chip is implemented under TSMC 0.18 μm, 1-poly, 6-metal CMOS technology and the core area of proposed LC-DCO is only 270 × 280 μm2. The full-chip post layout simulation results show 2.54 GHz oscillation frequency, 2.2mA current consumption and phase noise of -123 dBc/Hz at 1MHz offset.",
author = "Masahiro Ichihashi and Haruichi Kanaya",
year = "2018",
month = "11",
day = "1",
doi = "10.1587/transfun.E101.A.1907",
language = "English",
volume = "E101A",
pages = "1907--1914",
journal = "IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences",
issn = "0916-8508",
publisher = "Maruzen Co., Ltd/Maruzen Kabushikikaisha",
number = "11",

}

TY - JOUR

T1 - A low-power and GHz-Band LC-DCO directly drives 10mm on-chip clock distribution line in 0.18 μm CMOS

AU - Ichihashi, Masahiro

AU - Kanaya, Haruichi

PY - 2018/11/1

Y1 - 2018/11/1

N2 - High-speed clock distribution design is becoming increasingly difficult and challenging task due to the huge power consumption and jitter caused by large capacitive loading and multiple repeater stages. This paper proposes a novel low-power, GHz-band bufferless LC-DCO which directly drives 10 mm on-chip clock distribution line for high-speed serial links. The shared LC-tank structure between DCO frequency tuning capacitor and clock distribution line mitigate the frequency sensitivity and makes an energy-efficient, area-saving, high-speed operation possible. The test-chip is implemented under TSMC 0.18 μm, 1-poly, 6-metal CMOS technology and the core area of proposed LC-DCO is only 270 × 280 μm2. The full-chip post layout simulation results show 2.54 GHz oscillation frequency, 2.2mA current consumption and phase noise of -123 dBc/Hz at 1MHz offset.

AB - High-speed clock distribution design is becoming increasingly difficult and challenging task due to the huge power consumption and jitter caused by large capacitive loading and multiple repeater stages. This paper proposes a novel low-power, GHz-band bufferless LC-DCO which directly drives 10 mm on-chip clock distribution line for high-speed serial links. The shared LC-tank structure between DCO frequency tuning capacitor and clock distribution line mitigate the frequency sensitivity and makes an energy-efficient, area-saving, high-speed operation possible. The test-chip is implemented under TSMC 0.18 μm, 1-poly, 6-metal CMOS technology and the core area of proposed LC-DCO is only 270 × 280 μm2. The full-chip post layout simulation results show 2.54 GHz oscillation frequency, 2.2mA current consumption and phase noise of -123 dBc/Hz at 1MHz offset.

UR - http://www.scopus.com/inward/record.url?scp=85056077631&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85056077631&partnerID=8YFLogxK

U2 - 10.1587/transfun.E101.A.1907

DO - 10.1587/transfun.E101.A.1907

M3 - Article

VL - E101A

SP - 1907

EP - 1914

JO - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

JF - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

SN - 0916-8508

IS - 11

ER -