A low-power and GHz-Band LC-DCO directly drives 10mm on-chip clock distribution line in 0.18 μm CMOS

Masahiro Ichihashi, Haruichi Kanaya

研究成果: ジャーナルへの寄稿学術誌査読

1 被引用数 (Scopus)

抄録

High-speed clock distribution design is becoming increasingly difficult and challenging task due to the huge power consumption and jitter caused by large capacitive loading and multiple repeater stages. This paper proposes a novel low-power, GHz-band bufferless LC-DCO which directly drives 10 mm on-chip clock distribution line for high-speed serial links. The shared LC-tank structure between DCO frequency tuning capacitor and clock distribution line mitigate the frequency sensitivity and makes an energy-efficient, area-saving, high-speed operation possible. The test-chip is implemented under TSMC 0.18 μm, 1-poly, 6-metal CMOS technology and the core area of proposed LC-DCO is only 270 × 280 μm2. The full-chip post layout simulation results show 2.54 GHz oscillation frequency, 2.2mA current consumption and phase noise of -123 dBc/Hz at 1MHz offset.

本文言語英語
ページ(範囲)1907-1914
ページ数8
ジャーナルIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
E101A
11
DOI
出版ステータス出版済み - 11月 2018

!!!All Science Journal Classification (ASJC) codes

  • 信号処理
  • コンピュータ グラフィックスおよびコンピュータ支援設計
  • 電子工学および電気工学
  • 応用数学

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