A Low-Power and GHz-Band <i>LC</i>-DCO Directly Drives 10mm On-Chip Clock Distribution Line in 0.18µm CMOS

Masahiro Ichihashi, Haruichi Kanaya

研究成果: Contribution to journalArticle査読

抄録

<p>High-speed clock distribution design is becoming increasingly difficult and challenging task due to the huge power consumption and jitter caused by large capacitive loading and multiple repeater stages. This paper proposes a novel low-power, GHz-band bufferless <i>LC</i>-DCO which directly drives 10 mm on-chip clock distribution line for high-speed serial links. The shared <i>LC</i>-tank structure between DCO frequency tuning capacitor and clock distribution line mitigate the frequency sensitivity and makes an energy-efficient, area-saving, high-speed operation possible. The test-chip is implemented under TSMC 0.18µm, 1-poly, 6-metal CMOS technology and the core area of proposed <i>LC</i>-DCO is only 270×280µm<sup>2</sup>. The full-chip post layout simulation results show 2.54GHz oscillation frequency, 2.2mA current consumption and phase noise of -123dBc/Hz at 1MHz offset.</p>
本文言語英語
ページ(範囲)1907-1914
ページ数8
ジャーナルIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
101
11
DOI
出版ステータス出版済み - 2018

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