A memory power optimization technique for application specific embedded systems

Tohru Ishihara, Hiroto Yasuura

研究成果: Contribution to journalArticle査読

1 被引用数 (Scopus)

抄録

In this paper a novel application specific power optimization technique utilizing small instruction ROM which is placed between an instruction cache or a main program memory and CPU core is proposed. Our optimization technique targets embedded systems which assume the following: (i) instruction memories are organized by two on-chip memories a main program memory and a subprogram memory (ii) these two memories can be independently powered-up or powered-down by a special instruction of a core processor and (iii) a compiler optimizes an allocation of object code into these two memories so as to minimize average of read energy consumption. In many application programs only a few basic blocks are frequently executed. Therefore allocating these frequently executed basic blocks into low power subprogram memory leads significant energy reduction. Our experiments with actual ROM (Read Only Memory) modules created with 0.5/<m CMOS process technology' and MPEG2 codec program demonstrate significant energy reductions up to more than 50% at best case over the previous approach that applies only divided bit and word lines structure.

本文言語英語
ページ(範囲)2366-2374
ページ数9
ジャーナルIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
E82-A
11
出版ステータス出版済み - 1999

All Science Journal Classification (ASJC) codes

  • 信号処理
  • コンピュータ グラフィックスおよびコンピュータ支援設計
  • 電子工学および電気工学
  • 応用数学

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