A memory power optimization technique for application specific embedded systems

Tohru Ishihara, Hiroto Yasuura

研究成果: ジャーナルへの寄稿記事

1 引用 (Scopus)

抄録

In this paper a novel application specific power optimization technique utilizing small instruction ROM which is placed between an instruction cache or a main program memory and CPU core is proposed. Our optimization technique targets embedded systems which assume the following: (i) instruction memories are organized by two on-chip memories a main program memory and a subprogram memory (ii) these two memories can be independently powered-up or powered-down by a special instruction of a core processor and (iii) a compiler optimizes an allocation of object code into these two memories so as to minimize average of read energy consumption. In many application programs only a few basic blocks are frequently executed. Therefore allocating these frequently executed basic blocks into low power subprogram memory leads significant energy reduction. Our experiments with actual ROM (Read Only Memory) modules created with 0.5/<m CMOS process technology' and MPEG2 codec program demonstrate significant energy reductions up to more than 50% at best case over the previous approach that applies only divided bit and word lines structure.

元の言語英語
ページ(範囲)2366-2374
ページ数9
ジャーナルIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
E82-A
発行部数11
出版物ステータス出版済み - 1 1 1999

Fingerprint

Embedded systems
Embedded Systems
Optimization Techniques
Data storage equipment
ROM
MPEG-2
Application programs
Program processors
Energy
Energy utilization
Compiler
Cache
Energy Consumption
Chip
Optimise
Minimise
Module
Target
Line

All Science Journal Classification (ASJC) codes

  • Signal Processing
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering
  • Applied Mathematics

これを引用

A memory power optimization technique for application specific embedded systems. / Ishihara, Tohru; Yasuura, Hiroto.

:: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 巻 E82-A, 番号 11, 01.01.1999, p. 2366-2374.

研究成果: ジャーナルへの寄稿記事

@article{7cbdb3d60d734cc39b598548103d683a,
title = "A memory power optimization technique for application specific embedded systems",
abstract = "In this paper a novel application specific power optimization technique utilizing small instruction ROM which is placed between an instruction cache or a main program memory and CPU core is proposed. Our optimization technique targets embedded systems which assume the following: (i) instruction memories are organized by two on-chip memories a main program memory and a subprogram memory (ii) these two memories can be independently powered-up or powered-down by a special instruction of a core processor and (iii) a compiler optimizes an allocation of object code into these two memories so as to minimize average of read energy consumption. In many application programs only a few basic blocks are frequently executed. Therefore allocating these frequently executed basic blocks into low power subprogram memory leads significant energy reduction. Our experiments with actual ROM (Read Only Memory) modules created with 0.5/",
author = "Tohru Ishihara and Hiroto Yasuura",
year = "1999",
month = "1",
day = "1",
language = "English",
volume = "E82-A",
pages = "2366--2374",
journal = "IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences",
issn = "0916-8508",
publisher = "Maruzen Co., Ltd/Maruzen Kabushikikaisha",
number = "11",

}

TY - JOUR

T1 - A memory power optimization technique for application specific embedded systems

AU - Ishihara, Tohru

AU - Yasuura, Hiroto

PY - 1999/1/1

Y1 - 1999/1/1

N2 - In this paper a novel application specific power optimization technique utilizing small instruction ROM which is placed between an instruction cache or a main program memory and CPU core is proposed. Our optimization technique targets embedded systems which assume the following: (i) instruction memories are organized by two on-chip memories a main program memory and a subprogram memory (ii) these two memories can be independently powered-up or powered-down by a special instruction of a core processor and (iii) a compiler optimizes an allocation of object code into these two memories so as to minimize average of read energy consumption. In many application programs only a few basic blocks are frequently executed. Therefore allocating these frequently executed basic blocks into low power subprogram memory leads significant energy reduction. Our experiments with actual ROM (Read Only Memory) modules created with 0.5/

AB - In this paper a novel application specific power optimization technique utilizing small instruction ROM which is placed between an instruction cache or a main program memory and CPU core is proposed. Our optimization technique targets embedded systems which assume the following: (i) instruction memories are organized by two on-chip memories a main program memory and a subprogram memory (ii) these two memories can be independently powered-up or powered-down by a special instruction of a core processor and (iii) a compiler optimizes an allocation of object code into these two memories so as to minimize average of read energy consumption. In many application programs only a few basic blocks are frequently executed. Therefore allocating these frequently executed basic blocks into low power subprogram memory leads significant energy reduction. Our experiments with actual ROM (Read Only Memory) modules created with 0.5/

UR - http://www.scopus.com/inward/record.url?scp=0009604710&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0009604710&partnerID=8YFLogxK

M3 - Article

VL - E82-A

SP - 2366

EP - 2374

JO - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

JF - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

SN - 0916-8508

IS - 11

ER -