A novel capture-safety checking method for multi-clock designs and accuracy evaluation with delay capture circuits

Kohei Miyase, Masao Aso, Ryou Ootsuka, Xiaoqing Wen, Hiroshi Furukawa, Yuta Yamato, Kazunari Enokimoto, Seiji Kajihara

研究成果: Chapter in Book/Report/Conference proceedingConference contribution

2 被引用数 (Scopus)

抄録

Excessive capture power in at-speed scan testing may cause yield loss due to timing failures. Although reducing the number of clock domains that capture test responses simultaneously is a practical and scalable solution for reducing capture power, no available capture-safety checking metric can assess its effect in an accurate-enough manner, especially when multiple clock domains capture test responses in a short period of time. This paper proposes a novel CLEAR (CLock-Edge-Arrival-Relation-based) capture-safety checking method that, for the first time, takes clock edge arrival times for different clock domains into consideration. The accuracy and usefulness of the proposed method have been clearly demonstrated by simulation-based evaluation with the largest ITC'99 benchmark circuit as well as real-chip-based evaluation with an industrial chip embedded with on-chip delay measurement circuitry.

本文言語英語
ホスト出版物のタイトルProceedings - 2012 30th IEEE VLSI Test Symposium, VTS 2012
ページ197-202
ページ数6
DOI
出版ステータス出版済み - 2012
イベント2012 30th IEEE VLSI Test Symposium, VTS 2012 - Hyatt Maui, HI, 米国
継続期間: 4 23 20124 26 2012

出版物シリーズ

名前Proceedings of the IEEE VLSI Test Symposium

その他

その他2012 30th IEEE VLSI Test Symposium, VTS 2012
国/地域米国
CityHyatt Maui, HI
Period4/23/124/26/12

All Science Journal Classification (ASJC) codes

  • コンピュータ サイエンスの応用
  • 電子工学および電気工学

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