A novel Digital-to-Analog Converter (DAC) utilizing Tribonacci Series is presented in this paper. The ratios of successive weights are smaller than those of binary DAC and larger than those of unary DAC. The proposed DAC has the features that the DNL can be superior to that of a binary DAC and the INL can be superior to that of a unary DAC. In the proposed DAC on a 0.18 μm CMOS process, the number of logic gates can be achieved an around 52% reduction compared to that of the unary DAC.
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