A novel traffic engineering method using on-chip diorama network on dynamically reconfigurable processor DAPDNA-2

Shan Gao, Taku Kihara, Sho Shimizu, Yutaka Arakawa, Naoaki Yamanaka, Akifumi Watanabe

研究成果: Chapter in Book/Report/Conference proceedingConference contribution

4 引用 (Scopus)

抜粋

This paper proposes a novel traffic engineering method using on-chip diorama network that consists of virtual nodes and virtual links. The diorama network is implemented on reconfigurable processor DAPDNA-2. In these years, traffic engineering has widely researched to guarantee QoS (Quality of Service). The proposal is an experimental solution with the on-chip diorama network, where virtual links and virtual nodes are constructed by some PEs (processing elements). We obtain the realistic traffic fluctuation through the behavior of virtual packets exchanged on the on-chip diorama network. In this paper, as first trial to achieve our final goal, we implemented diorama network and confirmed basic path calculation, where both functions are an essential function of our algorithm. The diorama network traffic engineering can realize more sophisticated network design like adaptive traffic balancing or multi-metric design.

元の言語英語
ホスト出版物のタイトル2009 International Conference on High Performance Switching and Routing, HPSR 2009
DOI
出版物ステータス出版済み - 12 1 2009
外部発表Yes
イベント2009 International Conference on High Performance Switching and Routing, HPSR 2009 - Paris, フランス
継続期間: 6 22 20096 24 2009

出版物シリーズ

名前2009 International Conference on High Performance Switching and Routing, HPSR 2009

会議

会議2009 International Conference on High Performance Switching and Routing, HPSR 2009
フランス
Paris
期間6/22/096/24/09

All Science Journal Classification (ASJC) codes

  • Computer Networks and Communications
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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  • これを引用

    Gao, S., Kihara, T., Shimizu, S., Arakawa, Y., Yamanaka, N., & Watanabe, A. (2009). A novel traffic engineering method using on-chip diorama network on dynamically reconfigurable processor DAPDNA-2. : 2009 International Conference on High Performance Switching and Routing, HPSR 2009 [5307432] (2009 International Conference on High Performance Switching and Routing, HPSR 2009). https://doi.org/10.1109/HPSR.2009.5307432