A power reduction scheme for data buses by dynamic detection of active bits

Masanori Muroyama, Akihiko Hyodo, Takanori Okuma, Hiroto Yasuura

研究成果: ジャーナルへの寄稿記事

2 引用 (Scopus)

抄録

To transfer a small number, we inherently need a small number of bits. However all bit lines on a data bus change their status and redundant power is consumed. To reduce the redundant power consumption, we introduce a concept named active bit. In this paper, we propose a power reduction scheme for data buses using active bits. Suppressing switching activity of inactive bits, we can reduce redundant power consumption. We propose various power reduction techniques using active bits and the implementation methods. Experimental results illustrate up to 54.2% switching activity reduction.

元の言語英語
ページ(範囲)598-605
ページ数8
ジャーナルIEICE Transactions on Electronics
E87-C
発行部数4
出版物ステータス出版済み - 4 2004

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Electric power utilization

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

これを引用

A power reduction scheme for data buses by dynamic detection of active bits. / Muroyama, Masanori; Hyodo, Akihiko; Okuma, Takanori; Yasuura, Hiroto.

:: IEICE Transactions on Electronics, 巻 E87-C, 番号 4, 04.2004, p. 598-605.

研究成果: ジャーナルへの寄稿記事

Muroyama, Masanori ; Hyodo, Akihiko ; Okuma, Takanori ; Yasuura, Hiroto. / A power reduction scheme for data buses by dynamic detection of active bits. :: IEICE Transactions on Electronics. 2004 ; 巻 E87-C, 番号 4. pp. 598-605.
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