A prototype system for many-core architecture SMYLEref with FPGA evaluation boards

Son Truong Nguyen, Masaaki Kondo, Tomoya Hirao, Koji Inoue

研究成果: Contribution to journalArticle査読

1 被引用数 (Scopus)

抄録

Nowadays, the trend of developing micro-processor with hundreds of cores brings a promising prospect for embedded systems. Realizing a high performance and low power many-core processor is becoming a primary technical challenge. Generally, three major issues required to be resolved includes: 1) realizing efficient massively parallel processing, 2) reducing dynamic power consumption, and 3) improving software productivity. To deal with these issues, we propose a solution to use many lowperformance but small and very low-power cores to obtain very high performance, and develop a referential many-core architecture and a program development environment. This paper introduces a many-core architecture named SMYLEref and its prototype system with off-the-shelf FPGA evaluation boards. The initial evaluation results of several SPLASH2 benchmark programs conducted on our developed 128-core platform are also presented and discussed in this paper.

本文言語英語
ページ(範囲)1645-1653
ページ数9
ジャーナルIEICE Transactions on Information and Systems
E96-D
8
DOI
出版ステータス出版済み - 2013

All Science Journal Classification (ASJC) codes

  • ソフトウェア
  • ハードウェアとアーキテクチャ
  • コンピュータ ビジョンおよびパターン認識
  • 電子工学および電気工学
  • 人工知能

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