TY - GEN
T1 - A reconfigurable functional unit for an adaptive dynamic extensible processor
AU - Noori, Hamid
AU - Mehdipour, Farhad
AU - Murakami, Kazuaki
AU - Inoue, Koji
AU - Sahebzamani, Morteza
N1 - Copyright:
Copyright 2008 Elsevier B.V., All rights reserved.
PY - 2006
Y1 - 2006
N2 - This paper presents a reconfigurable functional unit (RFU) for an adaptive dynamic extensible processor. The processor can tune its extended instructions to the target applications, after chip-fabrication. The custom instructions (CIs) are generated deploying the hot basic blocks during the training mode. In the normal mode, CIs are executed on the RFU. A quantitative approach was used for designing the RFU. The RFU is a matrix of functional units with 8 inputs and 6 outputs. Performance is enhanced up to 1.25 using the proposed RFU for 22 applications of Mibench. This processor needs no extra opcodes for CIs, new compiler, source code modification and recompilation.
AB - This paper presents a reconfigurable functional unit (RFU) for an adaptive dynamic extensible processor. The processor can tune its extended instructions to the target applications, after chip-fabrication. The custom instructions (CIs) are generated deploying the hot basic blocks during the training mode. In the normal mode, CIs are executed on the RFU. A quantitative approach was used for designing the RFU. The RFU is a matrix of functional units with 8 inputs and 6 outputs. Performance is enhanced up to 1.25 using the proposed RFU for 22 applications of Mibench. This processor needs no extra opcodes for CIs, new compiler, source code modification and recompilation.
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U2 - 10.1109/FPL.2006.311313
DO - 10.1109/FPL.2006.311313
M3 - Conference contribution
AN - SCOPUS:38749127791
SN - 142440312X
SN - 9781424403127
T3 - Proceedings - 2006 International Conference on Field Programmable Logic and Applications, FPL
SP - 781
EP - 784
BT - Proceedings - 2006 International Conference on Field Programmable Logic and Applications, FPL
T2 - 2006 International Conference on Field Programmable Logic and Applications, FPL
Y2 - 28 August 2006 through 30 August 2006
ER -