A selective replacement method for timing-error-predicting flip-flops

Yuji Kunitake, Toshinori Sato, Hiroto Yasuura, Takanori Hayashida

研究成果: 著書/レポートタイプへの貢献会議での発言

2 引用 (Scopus)

抄録

The aggressive technology scaling brings us new challenges, such as parameter variations, soft errors, and device wearout. They increase unreliability of transistors and thus will become a serious problem in SoC designs. To attack these problems, spatial redundancy is commonly utilized. Based on the spatial redundancy, a lot of dual-sensing flip-flops (FFs) are proposed. These FFs require additional circuits consisting of a redundant FF and a comparator. Thus, they suffer large area overhead. In order to reduce the area overhead, this paper proposes a selective replacement method. We focus our attention on a timing-error-predicting FF, named canary FF and evaluate the selective replacement method. We apply it to two commercial processors, Toshiba's MeP and Renesas Electronics's M32R. In the case of MeP, the area overhead is reduced from 55% to 11%.

元の言語英語
ホスト出版物のタイトル54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011
DOI
出版物ステータス出版済み - 10 13 2011
イベント54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011 - Seoul, 大韓民国
継続期間: 8 7 20118 10 2011

出版物シリーズ

名前Midwest Symposium on Circuits and Systems
ISSN(印刷物)1548-3746

その他

その他54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011
大韓民国
Seoul
期間8/7/118/10/11

Fingerprint

Flip flop circuits
Redundancy
Transistors
Networks (circuits)

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

これを引用

Kunitake, Y., Sato, T., Yasuura, H., & Hayashida, T. (2011). A selective replacement method for timing-error-predicting flip-flops. : 54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011 [6026267] (Midwest Symposium on Circuits and Systems). https://doi.org/10.1109/MWSCAS.2011.6026267

A selective replacement method for timing-error-predicting flip-flops. / Kunitake, Yuji; Sato, Toshinori; Yasuura, Hiroto; Hayashida, Takanori.

54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011. 2011. 6026267 (Midwest Symposium on Circuits and Systems).

研究成果: 著書/レポートタイプへの貢献会議での発言

Kunitake, Y, Sato, T, Yasuura, H & Hayashida, T 2011, A selective replacement method for timing-error-predicting flip-flops. : 54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011., 6026267, Midwest Symposium on Circuits and Systems, 54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011, Seoul, 大韓民国, 8/7/11. https://doi.org/10.1109/MWSCAS.2011.6026267
Kunitake Y, Sato T, Yasuura H, Hayashida T. A selective replacement method for timing-error-predicting flip-flops. : 54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011. 2011. 6026267. (Midwest Symposium on Circuits and Systems). https://doi.org/10.1109/MWSCAS.2011.6026267
Kunitake, Yuji ; Sato, Toshinori ; Yasuura, Hiroto ; Hayashida, Takanori. / A selective replacement method for timing-error-predicting flip-flops. 54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011. 2011. (Midwest Symposium on Circuits and Systems).
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