A single cycle accessible two-level cache architecture for the energy consumption of embedded systems

Seiichiro Yamaguchi, Tohru Ishihara, Hiroto Yasuura

研究成果: 著書/レポートタイプへの貢献会議での発言

1 引用 (Scopus)

抄録

Employing a small L0-cache between an MPU core an L1-cache is one of the most promising approaches for reducing energy consumption of memory subsystems. Since the -cache is small, if there is a hit, the energy consumption will be. On the other hand, if there is a miss, one extra cycle is to access the L1-cache. This leads to a degradation of processor performance. For resolving this problem, a Single accessible Two-level Cache (STC) architecture is proposed this paper. This architecture makes it possible to access to both L0 and the L1 caches from an MPU core in a cycle. Experiments several benchmark programs demonstrate that STC architecture reduces the energy consumption of memory by 13% without any performance degradation compared the best results obtained by previous approaches.

元の言語英語
ホスト出版物のタイトル2008 International SoC Design Conference, ISOCC 2008
DOI
出版物ステータス出版済み - 12 1 2008
イベント2008 International SoC Design Conference, ISOCC 2008 - Busan, 大韓民国
継続期間: 11 24 200811 25 2008

出版物シリーズ

名前2008 International SoC Design Conference, ISOCC 2008
1

その他

その他2008 International SoC Design Conference, ISOCC 2008
大韓民国
Busan
期間11/24/0811/25/08

Fingerprint

Embedded systems
Energy utilization
Data storage equipment
Degradation
Experiments

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Software

これを引用

Yamaguchi, S., Ishihara, T., & Yasuura, H. (2008). A single cycle accessible two-level cache architecture for the energy consumption of embedded systems. : 2008 International SoC Design Conference, ISOCC 2008 [4815604] (2008 International SoC Design Conference, ISOCC 2008; 巻数 1). https://doi.org/10.1109/SOCDC.2008.4815604

A single cycle accessible two-level cache architecture for the energy consumption of embedded systems. / Yamaguchi, Seiichiro; Ishihara, Tohru; Yasuura, Hiroto.

2008 International SoC Design Conference, ISOCC 2008. 2008. 4815604 (2008 International SoC Design Conference, ISOCC 2008; 巻 1).

研究成果: 著書/レポートタイプへの貢献会議での発言

Yamaguchi, S, Ishihara, T & Yasuura, H 2008, A single cycle accessible two-level cache architecture for the energy consumption of embedded systems. : 2008 International SoC Design Conference, ISOCC 2008., 4815604, 2008 International SoC Design Conference, ISOCC 2008, 巻. 1, 2008 International SoC Design Conference, ISOCC 2008, Busan, 大韓民国, 11/24/08. https://doi.org/10.1109/SOCDC.2008.4815604
Yamaguchi S, Ishihara T, Yasuura H. A single cycle accessible two-level cache architecture for the energy consumption of embedded systems. : 2008 International SoC Design Conference, ISOCC 2008. 2008. 4815604. (2008 International SoC Design Conference, ISOCC 2008). https://doi.org/10.1109/SOCDC.2008.4815604
Yamaguchi, Seiichiro ; Ishihara, Tohru ; Yasuura, Hiroto. / A single cycle accessible two-level cache architecture for the energy consumption of embedded systems. 2008 International SoC Design Conference, ISOCC 2008. 2008. (2008 International SoC Design Conference, ISOCC 2008).
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