A soft error tolerance estimation method for sequential circuits

Masayoshi Yoshimura, Yusuke Akamine, Yusuke Matsunaga

研究成果: Chapter in Book/Report/Conference proceedingConference contribution

抄録

In advanced technology, soft error tolerance of VLSIs decreases. Soft errors might cause VLSIs to failure. However, there is no exact method to estimate soft error tolerance for sequential circuits of VLSIs. We propose an exact method to estimate soft error tolerance for sequential circuits. The failure due to soft errors in sequential circuits is defined by using the modified product machine. The behavior of the modified product machine is analyzed using Markov model strictly. We also propose two acceleration techniques to apply the exact method to larger scale circuits. Two acceleration techniques reduce the number of variables of simultaneous linear equations. We apply the proposed method to ISCAS'89 and MCNC benchmark circuits and estimate soft error tolerance for sequential circuits. Experimental results shows that two acceleration techniques reduce up to 10 times from its original execution time.

本文言語英語
ホスト出版物のタイトルProceedings - 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2011
ページ268-276
ページ数9
DOI
出版ステータス出版済み - 12 1 2011
イベント2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2011 - Vancouver, BC, カナダ
継続期間: 10 3 201110 5 2011

出版物シリーズ

名前Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
ISSN(印刷版)1550-5774

その他

その他2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2011
国/地域カナダ
CityVancouver, BC
Period10/3/1110/5/11

All Science Journal Classification (ASJC) codes

  • 工学(全般)

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