A test methodology for core-based system lsis

Makoto Sugihara, Hiroshi Date, Hiroto Yasuura

研究成果: ジャーナルへの寄稿記事

7 引用 (Scopus)

抄録

In this paper, we propose a test methodology for core-based system LSIs. Our test methodology aims to decrease testing time for core-based system LSIs. In our method, every core is supplied with several sets of test vectors. Every set of test vectors guarantees sufficient fault coverage. Each set of test vectors consists of two parts. One is based on built-in self-test (BIST) and the other is based on external testing. These sets of test vectors are designed to have différent ratio of BIST to external testing each other for every core. We can minimize testing time for core-based system LSIs by selecting from the given sets of test vectors for each core. The main contributions of this paper are summarized as follows. (i). BIST is efficiently combined with external testing to relax the limitation of the external primary inputs and outputs. (ii). External testing for one of cores and BISTs for the others are performed in parallel to reduce the total testing time. (iii). The testing time minimization problem for core-based system LSIs is formulated as a combinatorial optimization problem to select the optima! set of test vectors from given sets of test vectors for each core.

元の言語英語
ページ(範囲)2640-2645
ページ数6
ジャーナルIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
E81-A
発行部数12
出版物ステータス出版済み - 1 1 1998

Fingerprint

Built-in self test
Methodology
Testing
Built-in Self-test
Combinatorial optimization
Combinatorial Optimization Problem
Minimization Problem
Coverage
Fault
Sufficient
Minimise
Decrease
Output

All Science Journal Classification (ASJC) codes

  • Signal Processing
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering
  • Applied Mathematics

これを引用

A test methodology for core-based system lsis. / Sugihara, Makoto; Date, Hiroshi; Yasuura, Hiroto.

:: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 巻 E81-A, 番号 12, 01.01.1998, p. 2640-2645.

研究成果: ジャーナルへの寄稿記事

@article{8317226b47a24655b26c90b4c4840a34,
title = "A test methodology for core-based system lsis",
abstract = "In this paper, we propose a test methodology for core-based system LSIs. Our test methodology aims to decrease testing time for core-based system LSIs. In our method, every core is supplied with several sets of test vectors. Every set of test vectors guarantees sufficient fault coverage. Each set of test vectors consists of two parts. One is based on built-in self-test (BIST) and the other is based on external testing. These sets of test vectors are designed to have diff{\'e}rent ratio of BIST to external testing each other for every core. We can minimize testing time for core-based system LSIs by selecting from the given sets of test vectors for each core. The main contributions of this paper are summarized as follows. (i). BIST is efficiently combined with external testing to relax the limitation of the external primary inputs and outputs. (ii). External testing for one of cores and BISTs for the others are performed in parallel to reduce the total testing time. (iii). The testing time minimization problem for core-based system LSIs is formulated as a combinatorial optimization problem to select the optima! set of test vectors from given sets of test vectors for each core.",
author = "Makoto Sugihara and Hiroshi Date and Hiroto Yasuura",
year = "1998",
month = "1",
day = "1",
language = "English",
volume = "E81-A",
pages = "2640--2645",
journal = "IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences",
issn = "0916-8508",
publisher = "Maruzen Co., Ltd/Maruzen Kabushikikaisha",
number = "12",

}

TY - JOUR

T1 - A test methodology for core-based system lsis

AU - Sugihara, Makoto

AU - Date, Hiroshi

AU - Yasuura, Hiroto

PY - 1998/1/1

Y1 - 1998/1/1

N2 - In this paper, we propose a test methodology for core-based system LSIs. Our test methodology aims to decrease testing time for core-based system LSIs. In our method, every core is supplied with several sets of test vectors. Every set of test vectors guarantees sufficient fault coverage. Each set of test vectors consists of two parts. One is based on built-in self-test (BIST) and the other is based on external testing. These sets of test vectors are designed to have différent ratio of BIST to external testing each other for every core. We can minimize testing time for core-based system LSIs by selecting from the given sets of test vectors for each core. The main contributions of this paper are summarized as follows. (i). BIST is efficiently combined with external testing to relax the limitation of the external primary inputs and outputs. (ii). External testing for one of cores and BISTs for the others are performed in parallel to reduce the total testing time. (iii). The testing time minimization problem for core-based system LSIs is formulated as a combinatorial optimization problem to select the optima! set of test vectors from given sets of test vectors for each core.

AB - In this paper, we propose a test methodology for core-based system LSIs. Our test methodology aims to decrease testing time for core-based system LSIs. In our method, every core is supplied with several sets of test vectors. Every set of test vectors guarantees sufficient fault coverage. Each set of test vectors consists of two parts. One is based on built-in self-test (BIST) and the other is based on external testing. These sets of test vectors are designed to have différent ratio of BIST to external testing each other for every core. We can minimize testing time for core-based system LSIs by selecting from the given sets of test vectors for each core. The main contributions of this paper are summarized as follows. (i). BIST is efficiently combined with external testing to relax the limitation of the external primary inputs and outputs. (ii). External testing for one of cores and BISTs for the others are performed in parallel to reduce the total testing time. (iii). The testing time minimization problem for core-based system LSIs is formulated as a combinatorial optimization problem to select the optima! set of test vectors from given sets of test vectors for each core.

UR - http://www.scopus.com/inward/record.url?scp=0032305822&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0032305822&partnerID=8YFLogxK

M3 - Article

VL - E81-A

SP - 2640

EP - 2645

JO - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

JF - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

SN - 0916-8508

IS - 12

ER -