A thread-level parallelization of pairwise additive potential and force calculations suitable for current many-core architectures

Yoshimichi Ando; Soichiro Suzuki; Satoshi Ohshima; Tetsuya Sakashita; Masao Ogino; Takahiro Katagiri; Noriyuki Yoshii; Susumu Okazaki

doi:10.1007/s11227-018-2272-2

A thread-level parallelization of pairwise additive potential and force calculations suitable for current many-core architectures

Yoshimichi Ando, Soichiro Suzuki, Satoshi Ohshima, Tetsuya Sakashita, Masao Ogino, Takahiro Katagiri, Noriyuki Yoshii, Susumu Okazaki

研究成果: ジャーナルへの寄稿 › 学術誌 › 査読

4 被引用数 (Scopus)

本文言語	英語
ジャーナル	Journal of Supercomputing
DOI	https://doi.org/10.1007/s11227-018-2272-2
出版ステータス	出版済み - 2月 12 2018

文献へのアクセス

10.1007/s11227-018-2272-2

引用スタイル

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title = "A thread-level parallelization of pairwise additive potential and force calculations suitable for current many-core architectures",

author = "Yoshimichi Ando and Soichiro Suzuki and Satoshi Ohshima and Tetsuya Sakashita and Masao Ogino and Takahiro Katagiri and Noriyuki Yoshii and Susumu Okazaki",

year = "2018",

month = feb,

day = "12",

doi = "10.1007/s11227-018-2272-2",

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T1 - A thread-level parallelization of pairwise additive potential and force calculations suitable for current many-core architectures

AU - Ando, Yoshimichi

AU - Suzuki, Soichiro

AU - Ohshima, Satoshi

AU - Sakashita, Tetsuya

AU - Ogino, Masao

AU - Katagiri, Takahiro

AU - Yoshii, Noriyuki

AU - Okazaki, Susumu

PY - 2018/2/12

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DO - 10.1007/s11227-018-2272-2

M3 - Article

SN - 0920-8542

JO - Journal of Supercomputing

JF - Journal of Supercomputing

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