A tri-level 50MS/s 10-bit capacitive-DAC for Bluetooth applications

Daisuke Kanemoto, Keigo Oshiro, Keiji Yoshida, Haruichi Kanaya

研究成果: Chapter in Book/Report/Conference proceedingConference contribution

抜粋

This document summarizes, for the university design contest, a chip design of a low power dissipation and small die area 10-bit capacitive digital-to-analog converter (DAC) in a 0.18 μm CMOS process. Power dissipation of this chip is 350 μW including the output buffers. The die area is 0.081mm2.

元の言語英語
ホスト出版物のタイトル20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015
出版者Institute of Electrical and Electronics Engineers Inc.
ページ34-35
ページ数2
ISBN(電子版)9781479977925
DOI
出版物ステータス出版済み - 3 11 2015
イベント2015 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015 - Chiba, 日本
継続期間: 1 19 20151 22 2015

出版物シリーズ

名前20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015

その他

その他2015 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015
日本
Chiba
期間1/19/151/22/15

All Science Journal Classification (ASJC) codes

  • Computer Science Applications
  • Electrical and Electronic Engineering
  • Control and Systems Engineering
  • Modelling and Simulation

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  • これを引用

    Kanemoto, D., Oshiro, K., Yoshida, K., & Kanaya, H. (2015). A tri-level 50MS/s 10-bit capacitive-DAC for Bluetooth applications. : 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015 (pp. 34-35). [7058973] (20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASPDAC.2015.7058973