A tri-level 50MS/s 10-bit capacitive-DAC for Bluetooth applications

Daisuke Kanemoto, Keigo Oshiro, Keiji Yoshida, Haruichi Kanaya

研究成果: 著書/レポートタイプへの貢献会議での発言

抄録

This document summarizes, for the university design contest, a chip design of a low power dissipation and small die area 10-bit capacitive digital-to-analog converter (DAC) in a 0.18 μm CMOS process. Power dissipation of this chip is 350 μW including the output buffers. The die area is 0.081mm2.

元の言語英語
ホスト出版物のタイトル20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015
出版者Institute of Electrical and Electronics Engineers Inc.
ページ34-35
ページ数2
ISBN(電子版)9781479977925
DOI
出版物ステータス出版済み - 3 11 2015
イベント2015 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015 - Chiba, 日本
継続期間: 1 19 20151 22 2015

出版物シリーズ

名前20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015

その他

その他2015 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015
日本
Chiba
期間1/19/151/22/15

Fingerprint

Analog-to-digital Converter
Bluetooth
Digital to analog conversion
Dissipation
Energy dissipation
Chip
Die
Buffer
Output
Design
Universities

All Science Journal Classification (ASJC) codes

  • Computer Science Applications
  • Electrical and Electronic Engineering
  • Control and Systems Engineering
  • Modelling and Simulation

これを引用

Kanemoto, D., Oshiro, K., Yoshida, K., & Kanaya, H. (2015). A tri-level 50MS/s 10-bit capacitive-DAC for Bluetooth applications. : 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015 (pp. 34-35). [7058973] (20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASPDAC.2015.7058973

A tri-level 50MS/s 10-bit capacitive-DAC for Bluetooth applications. / Kanemoto, Daisuke; Oshiro, Keigo; Yoshida, Keiji; Kanaya, Haruichi.

20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015. Institute of Electrical and Electronics Engineers Inc., 2015. p. 34-35 7058973 (20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015).

研究成果: 著書/レポートタイプへの貢献会議での発言

Kanemoto, D, Oshiro, K, Yoshida, K & Kanaya, H 2015, A tri-level 50MS/s 10-bit capacitive-DAC for Bluetooth applications. : 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015., 7058973, 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015, Institute of Electrical and Electronics Engineers Inc., pp. 34-35, 2015 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015, Chiba, 日本, 1/19/15. https://doi.org/10.1109/ASPDAC.2015.7058973
Kanemoto D, Oshiro K, Yoshida K, Kanaya H. A tri-level 50MS/s 10-bit capacitive-DAC for Bluetooth applications. : 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015. Institute of Electrical and Electronics Engineers Inc. 2015. p. 34-35. 7058973. (20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015). https://doi.org/10.1109/ASPDAC.2015.7058973
Kanemoto, Daisuke ; Oshiro, Keigo ; Yoshida, Keiji ; Kanaya, Haruichi. / A tri-level 50MS/s 10-bit capacitive-DAC for Bluetooth applications. 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015. Institute of Electrical and Electronics Engineers Inc., 2015. pp. 34-35 (20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015).
@inproceedings{c021dc3785eb489c8e60b7c7b87c731a,
title = "A tri-level 50MS/s 10-bit capacitive-DAC for Bluetooth applications",
abstract = "This document summarizes, for the university design contest, a chip design of a low power dissipation and small die area 10-bit capacitive digital-to-analog converter (DAC) in a 0.18 μm CMOS process. Power dissipation of this chip is 350 μW including the output buffers. The die area is 0.081mm2.",
author = "Daisuke Kanemoto and Keigo Oshiro and Keiji Yoshida and Haruichi Kanaya",
year = "2015",
month = "3",
day = "11",
doi = "10.1109/ASPDAC.2015.7058973",
language = "English",
series = "20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "34--35",
booktitle = "20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015",
address = "United States",

}

TY - GEN

T1 - A tri-level 50MS/s 10-bit capacitive-DAC for Bluetooth applications

AU - Kanemoto, Daisuke

AU - Oshiro, Keigo

AU - Yoshida, Keiji

AU - Kanaya, Haruichi

PY - 2015/3/11

Y1 - 2015/3/11

N2 - This document summarizes, for the university design contest, a chip design of a low power dissipation and small die area 10-bit capacitive digital-to-analog converter (DAC) in a 0.18 μm CMOS process. Power dissipation of this chip is 350 μW including the output buffers. The die area is 0.081mm2.

AB - This document summarizes, for the university design contest, a chip design of a low power dissipation and small die area 10-bit capacitive digital-to-analog converter (DAC) in a 0.18 μm CMOS process. Power dissipation of this chip is 350 μW including the output buffers. The die area is 0.081mm2.

UR - http://www.scopus.com/inward/record.url?scp=84926452899&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84926452899&partnerID=8YFLogxK

U2 - 10.1109/ASPDAC.2015.7058973

DO - 10.1109/ASPDAC.2015.7058973

M3 - Conference contribution

AN - SCOPUS:84926452899

T3 - 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015

SP - 34

EP - 35

BT - 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015

PB - Institute of Electrical and Electronics Engineers Inc.

ER -