A VLSI chip set for a large scale parallel inference machine: PIM/m

Hirohisa Machida, Hideki Ando, Kenichi Yasuda, Kiyohiro Furutani, Hiroshi Nakashima, Yasutaka Takeda, Katsuto Nakajima, Masao Nakaya

研究成果: ジャーナルへの寄稿Conference article

抄録

Three VLSI chips which are a processor chip, a cache memory chip, and a network control chip for a highly parallel inference machine with capability of max 128 MRPS (Mega Reduction Per Second) have been developed. A processing element (PE) which consists of the processor chip and the cache memory chip has been designed to be suited for logic programming languages. The processor chip has been constructed in a submicron CMOS process teclhnologies. The cache memory chip implements a hardware support called "Trail Buffer" which is suitable for the execution of the Prolog-like languages. The network control chip makes it possible to connect 256 PES in a mesh network.

元の言語英語
記事番号5727431
ジャーナルProceedings of the Custom Integrated Circuits Conference
DOI
出版物ステータス出版済み - 12 1 1992
外部発表Yes
イベント14th Annual Custom Integrated Circuits Conference, CICC 1992 - Boston, MA, 米国
継続期間: 5 3 19925 6 1992

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Cache memory
Logic programming
Computer programming languages
Program processors
Hardware
Processing

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

これを引用

A VLSI chip set for a large scale parallel inference machine : PIM/m. / Machida, Hirohisa; Ando, Hideki; Yasuda, Kenichi; Furutani, Kiyohiro; Nakashima, Hiroshi; Takeda, Yasutaka; Nakajima, Katsuto; Nakaya, Masao.

:: Proceedings of the Custom Integrated Circuits Conference, 01.12.1992.

研究成果: ジャーナルへの寄稿Conference article

Machida, Hirohisa ; Ando, Hideki ; Yasuda, Kenichi ; Furutani, Kiyohiro ; Nakashima, Hiroshi ; Takeda, Yasutaka ; Nakajima, Katsuto ; Nakaya, Masao. / A VLSI chip set for a large scale parallel inference machine : PIM/m. :: Proceedings of the Custom Integrated Circuits Conference. 1992.
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