Accelerating SAT-based Boolean matching for heterogeneous FPGAs using one-hot encoding and CEGAR technique

研究成果: Chapter in Book/Report/Conference proceedingConference contribution

9 被引用数 (Scopus)

抄録

This paper describes two speed-up techniques for Boolean matching of LUT-based circuits. One is one-hot encoding technique for variables representing input assignments. Though it requires more variables than existing binary encoding technique, almost all added clauses using one-hot encoding are binary clauses, which are suitable for efficient Boolean constraint propagation. The other is CEGAR (counter example guided abstraction refinement) technique which reduces the CPU time significantly. With both techniques, we can solve Boolean matching problem with 9 input function in 20 milliseconds on average, which is faster than the existing algorithms more than one order of magnitude.

本文言語英語
ホスト出版物のタイトル20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015
出版社Institute of Electrical and Electronics Engineers Inc.
ページ255-260
ページ数6
ISBN(電子版)9781479977925
DOI
出版ステータス出版済み - 3 11 2015
イベント2015 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015 - Chiba, 日本
継続期間: 1 19 20151 22 2015

出版物シリーズ

名前20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015

その他

その他2015 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015
Country日本
CityChiba
Period1/19/151/22/15

All Science Journal Classification (ASJC) codes

  • Computer Science Applications
  • Electrical and Electronic Engineering
  • Control and Systems Engineering
  • Modelling and Simulation

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