Achievement of low parasitic resistance in Ge n-channel metal-oxide-semiconductor field-effect transistor using an embedded TiN-source/drain structure

Y. Nagatomi, T. Tateyama, S. Tanaka, K. Yamamoto, D. Wang, H. Nakashima

研究成果: ジャーナルへの寄稿記事

4 引用 (Scopus)

抄録

We investigated the source/drain (S/D) parasitic resistance (R P) of a Ge n-channel metal-oxide-semiconductor field-effect transistor (n-MOSFET) with TiN-S/D. The R P was as high as ∼1400 Ω, which is attributed to a very thin amorphous interlayer (a-IL) at a TiN/Ge interface. To solve this problem, n-MOSFETs with an embedded S/D structure were fabricated, of which the S/D was formed by the etching of a Ge layer using 0.03%-H2O2 solution followed by TiN sputter deposition. The electrical performances were investigated for devices with etching depths in the range of 2-22 nm. The devices with etching depths of 2-5 nm did not work. The devices with etching depths of 12-15 nm showed a quite normal transistor operation, and the R P was as low as ∼130 Ω, which is comparable to that of a p-MOSFET with PtGe-S/D. However, R Ps of the devices with etching depths of ∼22 nm was considerably high. The reason for these results is discussed on the basis of an a-IL formation at the sidewall of the engraved S/D region.

元の言語英語
記事番号035001
ジャーナルSemiconductor Science and Technology
32
発行部数3
DOI
出版物ステータス出版済み - 1 24 2017

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MOSFET devices
metal oxide semiconductors
Etching
field effect transistors
etching
interlayers
Sputter deposition
Transistors
transistors

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Materials Chemistry

これを引用

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abstract = "We investigated the source/drain (S/D) parasitic resistance (R P) of a Ge n-channel metal-oxide-semiconductor field-effect transistor (n-MOSFET) with TiN-S/D. The R P was as high as ∼1400 Ω, which is attributed to a very thin amorphous interlayer (a-IL) at a TiN/Ge interface. To solve this problem, n-MOSFETs with an embedded S/D structure were fabricated, of which the S/D was formed by the etching of a Ge layer using 0.03{\%}-H2O2 solution followed by TiN sputter deposition. The electrical performances were investigated for devices with etching depths in the range of 2-22 nm. The devices with etching depths of 2-5 nm did not work. The devices with etching depths of 12-15 nm showed a quite normal transistor operation, and the R P was as low as ∼130 Ω, which is comparable to that of a p-MOSFET with PtGe-S/D. However, R Ps of the devices with etching depths of ∼22 nm was considerably high. The reason for these results is discussed on the basis of an a-IL formation at the sidewall of the engraved S/D region.",
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AU - Nagatomi, Y.

AU - Tateyama, T.

AU - Tanaka, S.

AU - Yamamoto, K.

AU - Wang, D.

AU - Nakashima, H.

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