The memory bandwidth can dramatically be improved by means of stacking the main memory (DRAM) on processor cores and connecting them by wide on-chip buses composed of through silicon vias (TSVs). The 3D stacking makes it possible to reduce the cache miss penalty because large amount of data can be transferred from the main memory to the cache at a time. If a large cache line size is employed, we can expect the effect of prefetching. However, it might worsen the system performance if programs do not have enough spatial localities of memory references. To solve this problem, we introduce software-controllable variable line-size cache scheme. In this paper, we apply it to an L1 data cache with 3D stacked DRAM organization. In our evaluation, it is observed that our approach reduces the L1 data cache and stacked DRAM energy consumption up to 75%, compared to a conventional cache.
|ホスト出版物のタイトル||2009 International SoC Design Conference, ISOCC 2009|
|出版ステータス||出版済み - 12 1 2009|
|イベント||2009 International SoC Design Conference, ISOCC 2009 - Busan, 大韓民国|
継続期間: 11 22 2009 → 11 24 2009
|その他||2009 International SoC Design Conference, ISOCC 2009|
|Period||11/22/09 → 11/24/09|
All Science Journal Classification (ASJC) codes