TY - JOUR
T1 - An accelerating technique for SAT-based ATPG
AU - Matsunaga, Yusuke
PY - 2017/2
Y1 - 2017/2
N2 - This paper describes an accelerating technique for SAT based ATPG (automatic test pattern generation). The main idea of the proposed algorithm is representing more than one test generation problems as one CNF formula with introducing control variables, which reduces CNF generation time. Furthermore, learnt clauses of previously solved problems are effectively shared for other problems solving, so that the SAT solving time is also reduced. Experimental results show that the proposed algorithm runs more than 3 times faster than the original SAT-based ATPG algorithm.
AB - This paper describes an accelerating technique for SAT based ATPG (automatic test pattern generation). The main idea of the proposed algorithm is representing more than one test generation problems as one CNF formula with introducing control variables, which reduces CNF generation time. Furthermore, learnt clauses of previously solved problems are effectively shared for other problems solving, so that the SAT solving time is also reduced. Experimental results show that the proposed algorithm runs more than 3 times faster than the original SAT-based ATPG algorithm.
UR - http://www.scopus.com/inward/record.url?scp=85012113437&partnerID=8YFLogxK
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U2 - 10.2197/ipsjtsldm.10.39
DO - 10.2197/ipsjtsldm.10.39
M3 - Article
AN - SCOPUS:85012113437
VL - 10
SP - 39
EP - 44
JO - IPSJ Transactions on System LSI Design Methodology
JF - IPSJ Transactions on System LSI Design Methodology
SN - 1882-6687
ER -