An architecture framework for an adaptive extensible processor

Hamid Noori, Farhad Mehdipour, Kazuaki Murakami, Koji Inoue, Morteza Saheb Zamani

研究成果: Contribution to journalArticle査読

17 被引用数 (Scopus)

抄録

To improve the performance of embedded processors, an effective technique is collapsing critical computation subgraphs as application-specific instruction set extensions and executing them on custom functional units. The problem with this approach is the immense cost and the long times required to design a new processor for each application. As a solution to this issue, we propose an adaptive extensible processor in which custom instructions (CIs) are generated and added after chip-fabrication. To support this feature, custom functional units are replaced by a reconfigurable matrix of functional units (FUs). A systematic quantitative approach is used for determining the appropriate structure of the reconfigurable functional unit (RFU). We also introduce an integrated framework for generating mappable CIs on the RFU. Using this architecture, performance is improved by up to 1.33, with an average improvement of 1.16, compared to a 4-issue in-order RISC processor. By partitioning the configuration memory, detecting similar/subset CIs and merging small CIs, the size of the configuration memory is reduced by 40%.

本文言語英語
ページ(範囲)313-340
ページ数28
ジャーナルJournal of Supercomputing
45
3
DOI
出版ステータス出版済み - 9 2008

All Science Journal Classification (ASJC) codes

  • ソフトウェア
  • 理論的コンピュータサイエンス
  • 情報システム
  • ハードウェアとアーキテクチャ

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