抄録
This paper proposes a novel Behavioral Synthesis method that improves performance of synthesized circuits utilizing specialized functional units effectively. Specialized functional units (e.g. Multiply-Accumulator) are designed for specific operation patterns to achieve shorter delay and/or smaller area than cascaded basic functional units. Almost all conventional methods cannot use specialized functional units effectively under a total area constraint because of their less flexibility for resource sharing. The proposed method makes it possible to solve module selection, scheduling, and functional unit allocation problems utilizing specialized functional units in practical time with some heuristics, and to reduce the number of clock cycles under total area and clock cycle time constraints. Experimental results show that the proposed method has achieved up to 35% and on average 14% reduction of the number of cycles with specialized functional units in practical time.
本文言語 | 英語 |
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ホスト出版物のタイトル | 2008 Asia and South Pacific Design Automation Conference, ASP-DAC |
ページ | 32-35 |
ページ数 | 4 |
DOI | |
出版ステータス | 出版済み - 2008 |
イベント | 2008 Asia and South Pacific Design Automation Conference, ASP-DAC - Seoul, 韓国 継続期間: 3月 21 2008 → 3月 24 2008 |
その他
その他 | 2008 Asia and South Pacific Design Automation Conference, ASP-DAC |
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国/地域 | 韓国 |
City | Seoul |
Period | 3/21/08 → 3/24/08 |
!!!All Science Journal Classification (ASJC) codes
- 工学(全般)