An estimation of encryption LSI testability against scan-based attack

Masayoshi Yoshimura, Yuma Ito, Hiroto Yasuura

研究成果: Chapter in Book/Report/Conference proceedingConference contribution

抄録

Recently, encryption LSIs are embedded in a variety of digital products for security and copyright protection. Most LSIs including encryption LSIs have scan paths for manufacturing tests. However, there is a risk that the secret information is leaked through scan paths. It is necessary to prevent side channel attacks to encryption LSIs. In this paper, we show all the factors for scan-based attacks to encryption LSIs. We propose a countermeasure that encryption LSIs are added to controllability and observability as possible under the condition that encryption LSI does not have all the factors which are necessary for scanbased attacks. We insert various structures of scan paths in DES chips and estimate testability and security of DES chips In addition, we propose the countermeasure against the scan-based attacks, and estimate the countermeasure from the viewpoints of testability and security. We show the trade-off between testability and security for various structures of scan path. The proposed countermeasure can achieve about 98% of high fault efficiency with preventing scan-based attack.

本文言語英語
ホスト出版物のタイトルISCIT 2010 - 2010 10th International Symposium on Communications and Information Technologies
ページ727-731
ページ数5
DOI
出版ステータス出版済み - 12 1 2010
イベント2010 10th International Symposium on Communications and Information Technologies, ISCIT 2010 - Tokyo, 日本
継続期間: 10 26 201010 29 2010

出版物シリーズ

名前ISCIT 2010 - 2010 10th International Symposium on Communications and Information Technologies

その他

その他2010 10th International Symposium on Communications and Information Technologies, ISCIT 2010
国/地域日本
CityTokyo
Period10/26/1010/29/10

All Science Journal Classification (ASJC) codes

  • コンピュータ ネットワークおよび通信
  • 情報システム

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