An optimization technique for low-energy embedded memory systems

Tadayuki Matsumura, Tohru Ishihara, Hiroto Yasuura

研究成果: Contribution to journalArticle査読

1 被引用数 (Scopus)

抄録

On-chip memories generally use higher supply (VDD) and higher threshold (Vth) voltages than those of logic parts to improve the static noise margin and to suppress the static energy consumption. However, the higher VDD increases the dynamic energy consumption. This paper proposes a hybrid memory architecture which consists of the following two regions; (1) a dynamic energy conscious region which uses low VDD and Vth and (2) a static energy conscious region which uses high V DD and Vth. The proposed architecture is applied to a scratchpad memory. This paper also proposes an optimization problem for finding the optimal code allocation and the memory configuration simultaneously, which minimizes the total energy consumption of the memory under constraints of a static noise margin (SNM), a write margin (WM) and a memory access delay. The memory configuration is defined by a memory division ratio, a β ratio and a VDD. Experimental results demonstrate that the total energy consumption of our original 90 nm SRAM can be reduced by 62.9% at the best case with a 4.56% area overhead without degradations of SNM, WM and access delay.

本文言語英語
ページ(範囲)239-249
ページ数11
ジャーナルIPSJ Transactions on System LSI Design Methodology
2
DOI
出版ステータス出版済み - 2009

All Science Journal Classification (ASJC) codes

  • コンピュータ サイエンスの応用
  • 電子工学および電気工学

フィンガープリント

「An optimization technique for low-energy embedded memory systems」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

引用スタイル