Analysis and design method of ZCS DC-DC converter in consideration of the parasitic capacitance of switch and its effect on loss reduction

Takahiro Ota, Jun Imaoka, Masahito Shoyama, Hiroyuki Onishi, Shingo Nagaoka, Sadaharu Morishita

研究成果: Chapter in Book/Report/Conference proceedingConference contribution

抄録

This paper proposes a new design method to minimize the cause of parasitic oscillation in zero-current-switching (ZCS) DC-DC converter. The parasitic capacitance in switche is considered in circuit operation, a design of the ZCS DC-DC converter is optimized by proposed design method. With some prerequisites and assumptions, the waveform equations of the parasitic oscillations are analytically derived. The equations show the essential condition to suppress the parasitic oscillations and designing procedure of the auxiliary circuit. A 90 VDC/385 VDC, 300 W, operating 200 kHz prototype has been built and evaluated. The experimental results confirmed the validity and switch loss reduction effect of the proposed design method. The main switch loss has been measured approximately 37% smaller than conventional design method.

本文言語英語
ホスト出版物のタイトル2016 IEEE 2nd Annual Southern Power Electronics Conference, SPEC 2016
出版社Institute of Electrical and Electronics Engineers Inc.
ISBN(電子版)9781509015467
DOI
出版ステータス出版済み - 1 1 2016
イベント2nd IEEE Annual Southern Power Electronics Conference, SPEC 2016 - Auckland, ニュージ―ランド
継続期間: 12 5 201612 8 2016

出版物シリーズ

名前2016 IEEE 2nd Annual Southern Power Electronics Conference, SPEC 2016

その他

その他2nd IEEE Annual Southern Power Electronics Conference, SPEC 2016
国/地域ニュージ―ランド
CityAuckland
Period12/5/1612/8/16

All Science Journal Classification (ASJC) codes

  • エネルギー工学および電力技術
  • 電子工学および電気工学

フィンガープリント

「Analysis and design method of ZCS DC-DC converter in consideration of the parasitic capacitance of switch and its effect on loss reduction」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

引用スタイル