Analysis and design of diode physical limit bandwidth efficient rectification circuit for maximum flat efficiency, wide impedance, and efficiency bandwidths

Babita Gyawali, Samundra K. Thapa, Adel Barakat, Kuniaki Yoshitomi, Ramesh K. Pokharel

研究成果: Contribution to journalArticle査読

抄録

Generally, a conventional voltage doubler circuit possesses a large variation of its input impedance over the bandwidth, which results in limited bandwidth and low RF-dc conversion efficiency. A basic aspect for designing wideband voltage doubler rectifiers is the use of complex matching circuits to achieve decade and octave impedance and RF-dc conversion efficiency bandwidths. Still, the reported techniques till now have been accompanied by a large fluctuation of the RF-dc conversion efficiency over the operating bandwidth. In this paper, we propose a novel rectification circuit with minimal inter-stage matching that consists of a single short-circuit stub and a virtual battery, which contributes negligible losses and overcomes these existing problems. Consequently, the proposed rectifier circuit achieves a diode physical-limit-bandwidth efficient rectification. In other words, the rectification bandwidth, as well as the peak efficiency, are controlled by the length of the stub and the physical limitation of the diodes.

本文言語英語
論文番号19941
ジャーナルScientific reports
11
1
DOI
出版ステータス出版済み - 12 2021

All Science Journal Classification (ASJC) codes

  • 一般

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