Analysis of effects of input arrival time variations on on-chip bus power consumption

Masanori Muroyama, Tohru Ishihara, Hiroto Yasuura

研究成果: ジャーナルへの寄稿Conference article

1 引用 (Scopus)

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This paper describes analysis of on-chip bus power in the presence of arrival time variations of input signals. With shrinking process geometries, coupling power between neighboring bus lines has enlarged. The coupling power depends on not only signal transition type but also the relative signal transition time difference. For conventional dynamic power estimation, deterministic models of the time difference are assumed. We deal with nondeterministic models considering variations, because variations such as process variations cause the input arrival time variations. As a result of the time variations, power estimation error may increase. In our analysis and experiments, firstly impact of the time variations on the power consumption is analytically modeled. Then, it is demonstrated that certain types of bus coding techniques suppress the impact.

元の言語英語
ページ(範囲)62-71
ページ数10
ジャーナルLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
5349 LNCS
DOI
出版物ステータス出版済み - 3 11 2009
イベント18th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2008 - Lisbon, ポルトガル
継続期間: 9 10 20089 12 2008

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All Science Journal Classification (ASJC) codes

  • Theoretical Computer Science
  • Computer Science(all)

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