Analyzing the impact of data prefetching on chip multiprocessors

Naoto Fukumoto, Tomonobu Mihara, Inoue Koji, Kazuaki Murakami

研究成果: Chapter in Book/Report/Conference proceedingConference contribution

4 被引用数 (Scopus)

抄録

Data prefetching is a well known approach to compensating for poor memory performance, and has been employed in commercial processor chips. Although a number of prefetching techniques have so far been proposed, in many cases, they have assumed single-core architectures. In Chip Multiprocessor (or CMP) chips, there are some shared resources such as L2 caches, buses, and so on. Therefore, the effect of prefetching on CMP should be different from traditional single-core processors. In this paper, we analyze the effect of prefetching on CMP performance. This paper first classifies the impact of prefetches issued during program execution. Then, we discuss quantitatively the effect of prefetching to memory performance. The experimental results show that the negative effect of invalidation of prefetched cache blocks is very small. In addition, it is observed that the current prefetch algorithms do not exploit effectively the feature of CMPs, i.e. cache-to-cache on-chip data transfer.

本文言語英語
ホスト出版物のタイトル13th IEEE Asia-Pacific Computer Systems Architecture Conference, ACSAC 2008
DOI
出版ステータス出版済み - 11 17 2008
イベント13th IEEE Asia-Pacific Computer Systems Architecture Conference, ACSAC 2008 - Hsinchu, 台湾省、中華民国
継続期間: 8 4 20088 6 2008

出版物シリーズ

名前13th IEEE Asia-Pacific Computer Systems Architecture Conference, ACSAC 2008

その他

その他13th IEEE Asia-Pacific Computer Systems Architecture Conference, ACSAC 2008
国/地域台湾省、中華民国
CityHsinchu
Period8/4/088/6/08

All Science Journal Classification (ASJC) codes

  • ハードウェアとアーキテクチャ
  • 電子工学および電気工学

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