Area recovery under depth constraint for technology mapping for LUT-based FPGAs

Taiga Takata, Yusuke Matsunaga

研究成果: Contribution to journalArticle査読

2 被引用数 (Scopus)

抄録

This paper presents Cut Resubstitution; a heuristic algorithm for postprocessing of technology mapping for LUT-based FPGAs to minimize area under depth constraint. The concept of Cut Resubstitution is iterating local transformation of an LUT network with considering actual area reduction without using Boolean matching. Cut Resubstitution iterates the following process. At first, Cut Resubstitution substitutes several LUTs in current network in such a way that another LUT is to be redundant. Then Cut Resubstitution eliminates the redundant LUT from network. Experimental results show that a simple depth-minimum mapper followed by Cut Resubstitution generates network whose area is 7%,7%,10% smaller than that generated by DAOmap for maximum number of inputs of LUT 4,5,6 on average. Our method is similar or slightly faster than DAOmap.

本文言語英語
ページ(範囲)200-211
ページ数12
ジャーナルIPSJ Transactions on System LSI Design Methodology
2
DOI
出版ステータス出版済み - 2009

All Science Journal Classification (ASJC) codes

  • Computer Science Applications
  • Electrical and Electronic Engineering

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