抄録
In designing a digital circuit with a microprocessor, there are several simulation levels. Using a logic synthesis tool and a layout synthesis tool, a lower-level simulation model can be generated from a design RT level described in HDLs. There is trade-off between accuracy and speed of simulations. A lower-level simulation model can simulate more accurately. There is little support for generating high-level simulation models in which a human designer is required. In this paper, an algorithm is proposed for high-level simulation model generation and experimental results are shown.
| 元の言語 | 英語 |
|---|---|
| ページ（範囲） | 35-45 |
| ページ数 | 11 |
| ジャーナル | Electronics and Communications in Japan, Part III: Fundamental Electronic Science (English translation of Denshi Tsushin Gakkai Ronbunshi) |
| 巻 | 79 |
| 発行部数 | 5 |
| 出版物ステータス | 出版済み - 5 1 1996 |
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All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering
これを引用
Automatic generation of command level simulation model of a processor from RT level description. / Akaboshi, Hiroki; Yasuura, Hiroto.
：: Electronics and Communications in Japan, Part III: Fundamental Electronic Science (English translation of Denshi Tsushin Gakkai Ronbunshi), 巻 79, 番号 5, 01.05.1996, p. 35-45.研究成果: ジャーナルへの寄稿 › 記事
}
TY - JOUR
T1 - Automatic generation of command level simulation model of a processor from RT level description
AU - Akaboshi, Hiroki
AU - Yasuura, Hiroto
PY - 1996/5/1
Y1 - 1996/5/1
N2 - In designing a digital circuit with a microprocessor, there are several simulation levels. Using a logic synthesis tool and a layout synthesis tool, a lower-level simulation model can be generated from a design RT level described in HDLs. There is trade-off between accuracy and speed of simulations. A lower-level simulation model can simulate more accurately. There is little support for generating high-level simulation models in which a human designer is required. In this paper, an algorithm is proposed for high-level simulation model generation and experimental results are shown.
AB - In designing a digital circuit with a microprocessor, there are several simulation levels. Using a logic synthesis tool and a layout synthesis tool, a lower-level simulation model can be generated from a design RT level described in HDLs. There is trade-off between accuracy and speed of simulations. A lower-level simulation model can simulate more accurately. There is little support for generating high-level simulation models in which a human designer is required. In this paper, an algorithm is proposed for high-level simulation model generation and experimental results are shown.
UR - http://www.scopus.com/inward/record.url?scp=0030141749&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0030141749&partnerID=8YFLogxK
M3 - Article
AN - SCOPUS:0030141749
VL - 79
SP - 35
EP - 45
JO - Electronics and Communications in Japan, Part III: Fundamental Electronic Science (English translation of Denshi Tsushin Gakkai Ronbunshi)
JF - Electronics and Communications in Japan, Part III: Fundamental Electronic Science (English translation of Denshi Tsushin Gakkai Ronbunshi)
SN - 1042-0967
IS - 5
ER -