Automatic generation of command level simulation model of a processor from RT level description

Hiroki Akaboshi, Hiroto Yasuura

研究成果: Contribution to journalArticle査読

抄録

In designing a digital circuit with a microprocessor, there are several simulation levels. Using a logic synthesis tool and a layout synthesis tool, a lower-level simulation model can be generated from a design RT level described in HDLs. There is trade-off between accuracy and speed of simulations. A lower-level simulation model can simulate more accurately. There is little support for generating high-level simulation models in which a human designer is required. In this paper, an algorithm is proposed for high-level simulation model generation and experimental results are shown.

本文言語英語
ページ(範囲)35-46
ページ数12
ジャーナルElectronics and Communications in Japan, Part III: Fundamental Electronic Science (English translation of Denshi Tsushin Gakkai Ronbunshi)
79
5
DOI
出版ステータス出版済み - 5 1996

All Science Journal Classification (ASJC) codes

  • 電子工学および電気工学

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