In designing a digital circuit with a microprocessor, there are several simulation levels. Using a logic synthesis tool and a layout synthesis tool, a lower-level simulation model can be generated from a design RT level described in HDLs. There is trade-off between accuracy and speed of simulations. A lower-level simulation model can simulate more accurately. There is little support for generating high-level simulation models in which a human designer is required. In this paper, an algorithm is proposed for high-level simulation model generation and experimental results are shown.
|ジャーナル||Electronics and Communications in Japan, Part III: Fundamental Electronic Science (English translation of Denshi Tsushin Gakkai Ronbunshi)|
|出版ステータス||出版済み - 5 1996|
All Science Journal Classification (ASJC) codes