TY - JOUR
T1 - Automatic generation of command level simulation model of a processor from RT level description
AU - Akaboshi, Hiroki
AU - Yasuura, Hiroto
PY - 1996/5
Y1 - 1996/5
N2 - In designing a digital circuit with a microprocessor, there are several simulation levels. Using a logic synthesis tool and a layout synthesis tool, a lower-level simulation model can be generated from a design RT level described in HDLs. There is trade-off between accuracy and speed of simulations. A lower-level simulation model can simulate more accurately. There is little support for generating high-level simulation models in which a human designer is required. In this paper, an algorithm is proposed for high-level simulation model generation and experimental results are shown.
AB - In designing a digital circuit with a microprocessor, there are several simulation levels. Using a logic synthesis tool and a layout synthesis tool, a lower-level simulation model can be generated from a design RT level described in HDLs. There is trade-off between accuracy and speed of simulations. A lower-level simulation model can simulate more accurately. There is little support for generating high-level simulation models in which a human designer is required. In this paper, an algorithm is proposed for high-level simulation model generation and experimental results are shown.
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U2 - 10.1002/ecjc.4430790504
DO - 10.1002/ecjc.4430790504
M3 - Article
AN - SCOPUS:0030141749
VL - 79
SP - 35
EP - 46
JO - Electronics and Communications in Japan, Part III: Fundamental Electronic Science (English translation of Denshi Tsushin Gakkai Ronbunshi)
JF - Electronics and Communications in Japan, Part III: Fundamental Electronic Science (English translation of Denshi Tsushin Gakkai Ronbunshi)
SN - 1042-0967
IS - 5
ER -