Basic experimentation on accuracy of power estimation for CMOS VLSI circuits

Tohru Ishihara, Hiroto Yasuura

研究成果: Contribution to conferencePaper査読

抄録

In this paper, we discuss on accuracy of several kinds of power dissipation model for CMOS VLSI circuits. Some researchers have proposed several efficient power estimation methods for CMOS circuits [1][2][3][4]. However, we do not know how accurate they are because we have not established a method to compare the estimated results of power consumption with that of actual VLSI chip. To evaluate the accuracy of several kind of power dissipation model such as chip-level, block-level and gate-level etc., we examined as follows: (i) Measuring power consumption of actual microprocessors. (ii) Estimating power consumption with several kinds of power dissipation model. (iii) Comparing (i) with (ii). The experimental results show as follows: (1) Power estimation at gate level is accurate enough. (2) Estimating power of a clock tree independently makes estimation more accurate.

本文言語英語
ページ117-120
ページ数4
出版ステータス出版済み - 12 1 1996
イベントProceedings of the 1996 International Symposium on Low Power Electronics and Design - Monterey, CA, USA
継続期間: 8 12 19968 14 1996

その他

その他Proceedings of the 1996 International Symposium on Low Power Electronics and Design
CityMonterey, CA, USA
Period8/12/968/14/96

All Science Journal Classification (ASJC) codes

  • 電子工学および電気工学
  • 電子材料、光学材料、および磁性材料

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