Behavioral verification of cpus using functional information extraction

The information extraction techniques which transform the description at the logic circuit level in the LSI design process into the description at the functional level are important. The authors have been studying the automatic transformation technique. By combining that technique with the technique for automatic logic synthesis which is now being developed, it is expected that the descriptions at the logic circuit level and the functional description can be transformed to each other. This will help to construct the integrated CAD system. The feature of the method proposed in this paper is that the arithmetic operation functions and the functions at the RT level can be extracted from the tremendous amount of complex circuit descriptions and the results are represented in a simple and clear form. Consequently, the method is especially suited to the behavior verification of the circuits, such as CPUs. In this paper, the object of consideration is limited to the circuits in the CPU system and the application of the functional information extraction technique to the design verification is discussed. Since the behavior description for a CPU is given in a simple and clear form, using the instruction code table or state transition table, the design verification is easy by a visual comparison of the extracted functional description. The complex logic functions in the control circuit are compared using BDD. An actual example of verification is shown in this paper for the 8‐bit microprocessor, and it is demonstrated that a practical processing is realized from the viewpoints of required time and memory capacity.