Border-trap characterization for Ge gate stacks using deep-level transient spectroscopy

Hiroshi Nakashima, Wei Chen Wen, Keisuke Yamamoto, Dong Wang

研究成果: 著書/レポートタイプへの貢献会議での発言

抜粋

A border trap (BT) evaluation method was established for SiO2/GeO2Ge gate stacks by using deep-level transient spectroscopy with a lock-in integrator. Ge metal-oxide-semiconductor capacitors (MOSCAPs) with SiCVGeCVGe gate stacks were fabricated by post-passivation thermal oxidation. The interface trap (IT) and BT signals were successfully separated based on their different dependences on the intensity of injection pulses. By using p-type MOSCAPs, BTs at the position of 0.4 nm from GeO2Ge interface were measured. The energy of these BTs was centralized at the position near to the valence band edge of Ge, and the density (Nbt) was in the range of 1017-1018 cm-3. For n-type MOSCAPs, BTs at the position range of 2.8-3.4 nm from the GeO2/Ge interface were measured. The energy of these BTs were distributed in a relatively wide range near to the conduction band edge of Ge, and the Nbt was approximately one order of magnitude higher than those for p-MOSCAPs. We also found that Al post metallization annealing can passivate both ITs and BTs near to the valence band edge of Ge but not those near to the conduction band edge.

元の言語英語
ホスト出版物のタイトルSemiconductor Process Integration 11
編集者J. Murota, C. Claeys, H. Iwai, M. Tao, S. Deleonibus, A. Mai, K. Shiojima, Y. Cao
出版者Electrochemical Society Inc.
ページ3-10
ページ数8
エディション4
ISBN(電子版)9781607685395
DOI
出版物ステータス出版済み - 1 1 2019
イベント11th Symposium on Semiconductor Process Integration - 236th ECS Meeting - Atlanta, 米国
継続期間: 10 13 201910 17 2019

出版物シリーズ

名前ECS Transactions
番号4
92
ISSN(印刷物)1938-6737
ISSN(電子版)1938-5862

会議

会議11th Symposium on Semiconductor Process Integration - 236th ECS Meeting
米国
Atlanta
期間10/13/1910/17/19

    フィンガープリント

All Science Journal Classification (ASJC) codes

  • Engineering(all)

これを引用

Nakashima, H., Wen, W. C., Yamamoto, K., & Wang, D. (2019). Border-trap characterization for Ge gate stacks using deep-level transient spectroscopy. : J. Murota, C. Claeys, H. Iwai, M. Tao, S. Deleonibus, A. Mai, K. Shiojima, ... Y. Cao (版), Semiconductor Process Integration 11 (4 版, pp. 3-10). (ECS Transactions; 巻数 92, 番号 4). Electrochemical Society Inc.. https://doi.org/10.1149/09204.0003ecsti