This paper comparatively discusses soft error immunity of silicon on thin BOX (SOTB) SRAM and conventional bulk SRAM presenting neutron- and muon-induced soft error rates (SER) in 65-nm 6T SRAM over a wide range of supply voltages. The results show that the neutron-induced multiple cell upset (MCU) rates of SOTB at 0.4 V and 1.0 V are 0.01 times and 0.003 times lower than those of bulk at 0.4 V and 1.0 V, respectively. In advanced bulk low-voltage SRAM, protons can be dominant secondary particles, which brings drastic SER elevation, but this will not arise in SOTB SRAM due to its thin SOI layer. We also characterized the immunity to positive and negative muons. We observed negative muon induced more upsets due to muon capture process. We also confirmed that SOTB SRAM was more robust to muon than bulk SRAM.