Characterizing soft error rates of 65-nm SOTB and bulk SRAMs with muon and neutron beams

Masanori Hashimoto, Wang Liao, Seiya Manabe, Yukinobu Watanabe

研究成果: 著書/レポートタイプへの貢献会議での発言

抄録

This paper comparatively discusses soft error immunity of silicon on thin BOX (SOTB) SRAM and conventional bulk SRAM presenting neutron- and muon-induced soft error rates (SER) in 65-nm 6T SRAM over a wide range of supply voltages. The results show that the neutron-induced multiple cell upset (MCU) rates of SOTB at 0.4 V and 1.0 V are 0.01 times and 0.003 times lower than those of bulk at 0.4 V and 1.0 V, respectively. In advanced bulk low-voltage SRAM, protons can be dominant secondary particles, which brings drastic SER elevation, but this will not arise in SOTB SRAM due to its thin SOI layer. We also characterized the immunity to positive and negative muons. We observed negative muon induced more upsets due to muon capture process. We also confirmed that SOTB SRAM was more robust to muon than bulk SRAM.

元の言語英語
ホスト出版物のタイトル2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018
出版者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子版)9781538676264
DOI
出版物ステータス出版済み - 2 11 2019
イベント2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018 - Burlingame, 米国
継続期間: 10 15 201810 18 2018

出版物シリーズ

名前2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018

会議

会議2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018
米国
Burlingame
期間10/15/1810/18/18

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Neutron beams
Static random access storage
neutron beams
Silicon
muons
silicon
immunity
neutrons
Neutrons
SOI (semiconductors)
low voltage
Electric potential
Protons
protons
electric potential
cells

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality
  • Electronic, Optical and Magnetic Materials
  • Instrumentation

これを引用

Hashimoto, M., Liao, W., Manabe, S., & Watanabe, Y. (2019). Characterizing soft error rates of 65-nm SOTB and bulk SRAMs with muon and neutron beams. : 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018 [8640144] (2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/S3S.2018.8640144

Characterizing soft error rates of 65-nm SOTB and bulk SRAMs with muon and neutron beams. / Hashimoto, Masanori; Liao, Wang; Manabe, Seiya; Watanabe, Yukinobu.

2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018. Institute of Electrical and Electronics Engineers Inc., 2019. 8640144 (2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018).

研究成果: 著書/レポートタイプへの貢献会議での発言

Hashimoto, M, Liao, W, Manabe, S & Watanabe, Y 2019, Characterizing soft error rates of 65-nm SOTB and bulk SRAMs with muon and neutron beams. : 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018., 8640144, 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018, Institute of Electrical and Electronics Engineers Inc., 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018, Burlingame, 米国, 10/15/18. https://doi.org/10.1109/S3S.2018.8640144
Hashimoto M, Liao W, Manabe S, Watanabe Y. Characterizing soft error rates of 65-nm SOTB and bulk SRAMs with muon and neutron beams. : 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018. Institute of Electrical and Electronics Engineers Inc. 2019. 8640144. (2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018). https://doi.org/10.1109/S3S.2018.8640144
Hashimoto, Masanori ; Liao, Wang ; Manabe, Seiya ; Watanabe, Yukinobu. / Characterizing soft error rates of 65-nm SOTB and bulk SRAMs with muon and neutron beams. 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018. Institute of Electrical and Electronics Engineers Inc., 2019. (2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018).
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abstract = "This paper comparatively discusses soft error immunity of silicon on thin BOX (SOTB) SRAM and conventional bulk SRAM presenting neutron- and muon-induced soft error rates (SER) in 65-nm 6T SRAM over a wide range of supply voltages. The results show that the neutron-induced multiple cell upset (MCU) rates of SOTB at 0.4 V and 1.0 V are 0.01 times and 0.003 times lower than those of bulk at 0.4 V and 1.0 V, respectively. In advanced bulk low-voltage SRAM, protons can be dominant secondary particles, which brings drastic SER elevation, but this will not arise in SOTB SRAM due to its thin SOI layer. We also characterized the immunity to positive and negative muons. We observed negative muon induced more upsets due to muon capture process. We also confirmed that SOTB SRAM was more robust to muon than bulk SRAM.",
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