Charge build-up and its reduction in plasma cleaning process

Kiyoshi Arita, Kazuhiro Noda, Tanemasa Asano

研究成果: 会議への寄与タイプ学会誌査読

6 被引用数 (Scopus)

抄録

Charge build-up in plasma cleaning process has been investigated from the view points of the plasma uniformity, gas species and pressure, plasma exposure time, anode-cathode distance and substrate (circuit board) configuration. The spatial distribution of plasma parameters in plasma cleaning was diagnosed using a Langmuir probe. The charge build-up was evaluated using metal/nitride/oxide silicon (MNOS) capacitors and metal/oxide/silicon (MOS) capacitors. Gases such as Ar, Ar+H2, Xe and O2 have been investigated. It has been found that the spatial distribution of plasma parameters is uniform, and that the charge build-up in the plasma cleaning is negligibly small as far as test chips are placed without substrates. Use of substrates was found to increase the amount of the charge build-up. The charge build-up was found to depend on size, material and structure of the substrate. It was found that the plasma cleaning with substrates having a conductive surface film such as plated gold film resulted in considerable charge build-up. We found that use of insulator mask or insulating die-bonding paste was very effective to minimize the charge build-up.

本文言語英語
ページ92-97
ページ数6
出版ステータス出版済み - 1998
イベントProceedings of the 1998 22nd IEEE/CPMT International Electronics Manufacturing Technology Symposium - Berlin, Ger
継続期間: 4月 27 19984月 29 1998

その他

その他Proceedings of the 1998 22nd IEEE/CPMT International Electronics Manufacturing Technology Symposium
CityBerlin, Ger
Period4/27/984/29/98

!!!All Science Journal Classification (ASJC) codes

  • 産業および生産工学
  • 電子工学および電気工学

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