Chip organization of bloch line memory

T. Suzuki, H. Asada, K. Matsuyama, E. Fujita, Y. Saegusa, K. Morikawa, K. Fujimoto, M. Shigenobu, K. Nakashi, B. Takamatsu, S. Konishi

研究成果: Contribution to journalArticle査読

37 被引用数 (Scopus)

抄録

A detailed and practical chip organization of Bloch line memory is proposed on the basis of preliminary experiments and computer simulations, The major line - minor loop organization is composed of two levels zigzag conductors to propagate bubbles (major line) and stripe domain walls surrounding grooved region where the epitaxial garnet layer is completely etched (minor loops), The garnet film thickness is chosen as one half of the usual bubble memory chip, which reduces the magneto-static attractive force between bubbles and between Bloch line pairs, and is preferable for Bloch line potential well generation to define bit position. New practical methods for VBL read-write operation are established by simulations and experiments.

本文言語英語
ページ(範囲)784-789
ページ数6
ジャーナルIEEE Transactions on Magnetics
22
5
DOI
出版ステータス出版済み - 9 1986

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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