Chip organization of bloch line memory

T. Suzuki, H. Asada, Kimihide Matsuyama, E. Fujita, Y. Saegusa, K. Morikawa, K. Fujimoto, M. Shigenobu, K. Nakashi, B. Takamatsu, S. Konishi

研究成果: ジャーナルへの寄稿記事

37 引用 (Scopus)

抄録

A detailed and practical chip organization of Bloch line memory is proposed on the basis of preliminary experiments and computer simulations, The major line - minor loop organization is composed of two levels zigzag conductors to propagate bubbles (major line) and stripe domain walls surrounding grooved region where the epitaxial garnet layer is completely etched (minor loops), The garnet film thickness is chosen as one half of the usual bubble memory chip, which reduces the magneto-static attractive force between bubbles and between Bloch line pairs, and is preferable for Bloch line potential well generation to define bit position. New practical methods for VBL read-write operation are established by simulations and experiments.

元の言語英語
ページ(範囲)784-789
ページ数6
ジャーナルIEEE Transactions on Magnetics
22
発行部数5
DOI
出版物ステータス出版済み - 1 1 1986

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Garnets
Magnetic bubble memories
Data storage equipment
Domain walls
Film thickness
Experiments
Computer simulation

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

これを引用

Suzuki, T., Asada, H., Matsuyama, K., Fujita, E., Saegusa, Y., Morikawa, K., ... Konishi, S. (1986). Chip organization of bloch line memory. IEEE Transactions on Magnetics, 22(5), 784-789. https://doi.org/10.1109/TMAG.1986.1064520

Chip organization of bloch line memory. / Suzuki, T.; Asada, H.; Matsuyama, Kimihide; Fujita, E.; Saegusa, Y.; Morikawa, K.; Fujimoto, K.; Shigenobu, M.; Nakashi, K.; Takamatsu, B.; Konishi, S.

:: IEEE Transactions on Magnetics, 巻 22, 番号 5, 01.01.1986, p. 784-789.

研究成果: ジャーナルへの寄稿記事

Suzuki, T, Asada, H, Matsuyama, K, Fujita, E, Saegusa, Y, Morikawa, K, Fujimoto, K, Shigenobu, M, Nakashi, K, Takamatsu, B & Konishi, S 1986, 'Chip organization of bloch line memory', IEEE Transactions on Magnetics, 巻. 22, 番号 5, pp. 784-789. https://doi.org/10.1109/TMAG.1986.1064520
Suzuki T, Asada H, Matsuyama K, Fujita E, Saegusa Y, Morikawa K その他. Chip organization of bloch line memory. IEEE Transactions on Magnetics. 1986 1 1;22(5):784-789. https://doi.org/10.1109/TMAG.1986.1064520
Suzuki, T. ; Asada, H. ; Matsuyama, Kimihide ; Fujita, E. ; Saegusa, Y. ; Morikawa, K. ; Fujimoto, K. ; Shigenobu, M. ; Nakashi, K. ; Takamatsu, B. ; Konishi, S. / Chip organization of bloch line memory. :: IEEE Transactions on Magnetics. 1986 ; 巻 22, 番号 5. pp. 784-789.
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